Planar solid oxide fuel cells (SOFCs) were designed, fabricated and characterized in order to develop a (1) cost-effective method for fabrication of thin electrolyte layers, (2) hermetic sealing and (3) stable interconnects. Electrophoretic deposition (EPD) was discovered to be an excellent method for fabricating dense electrolyte layers of about 5m thick on porous non-conducting substrates. The EPD process was thoroughly studied from proof-of-concept to statistical reproducibility, deposition mechanism, modeling and process optimization. Deposition on non-conducting substrates was found to follow many of the same fundamental trends as that on conductive substrates except for the voltage efficiency and detailed charge transfer mechanism. Eventually, the process was optimized such that an SOFC was fabricated that achieved 1.1W/cm2 at 850C. Further, a novel sealless planar SOFC was designed that incorporates a hermetic interface between the electrolyte and interconnect similar to tubular and honeycomb designs. The hermetic interface successfully acted as a blocking electrode under DC polarization, indicating its potential to act as a sealant. Leakage rates across the interface were 0.027sccm at 750c, similar to polycrystalline mica seals. Through a process of tape casting and lamination, a two-cell stack without sealant was fabricated and achieved a power density of 75mW/cm2 at 750C. Finally, the degradation rate of silver and silver-based interconnects was studied under static and dual-atmosphere conditions. Corrosion of silver grain boundaries along with sublimation losses results in the formation of large pores, resulting in up to 30 of anode oxidation after 8hrs testing at 750c. Further stability studies indicated that silver-based interconnects would be better suited for applications at operating temperatures less than 650C.

Experimental investigations of high temperature industrial processes, for example the melting and smelting processes taking place inside furnaces, are complicated by the high temperatures and the chemically reactive environment in which they take place. Fortunately, mathematical models can be used in conjunction with the limited experimental results that are available to gain insight into these high temperature processes. However, mathematical models of high temperature processes require high temperature material properties, which are difficult to measure experimentally since container materials are often unable to withstand high enough temperatures, and sample contamination often occurs. These difficulties can be overcome by employing containerless processing techniques such as electromagnetic levitation melting to allow for characterisation of high temperature material properties. Efficient design of electromagnetic levitation cells is challenging since the effects of changes in coil design, sample size and sample material on levitation force and sample temperature are not yet well understood. In this work a numerical model of the electromagnetic levitation cell is implemented and used to investigate the sensitivity of levitation cell operation to variations in coil design, sample material and sample size. Various levitation cell modelling methods in literature are reviewed and a suitable model is chosen, adapted for the current application, and implemented in Python. The finite volume electromagnetic component of the model is derived from Maxwell’s equations, while heat transfer is modelled using a lumped parameter energy balance based on the first law of thermodynamics. The implemented model is verified for a simple case with a known analytical solution, and validated against published experimental results. It is found that a calibrated model can successfully predict the lifting force inside the levitation cell, as well as the sample temperature at low coil currents. The validated model is used to characterise the operation of a levitation cell for a number of different sample materials and sample sizes, and for variations in coil geometry and coil current. The model can be used in this way to investigate a variety of cases and hence to support experimental levitation cell design. Based on model results, a number of operating procedure recommendations are also made. / Dissertation (MEng)--University of Pretoria, 2016. / Mechanical and Aeronautical Engineering / MEng / Unrestricted

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

The aim of this thesis was to describe how a manual assembly process of polycarbonate sheets for heat exchangers can be automated with an industrial robot. The objectives were to design suitable robot cell concepts and simulate them to describe how the automated process could be done and to present which machines and equipment that could be used. Additionally, productivity rates and investment costs was to be calculated.The project started with a situation assessment and a literature review. Experts and suppliers of robotic equipment were consulted, and the results served as a basis for the concept generation process. Several concept ideas were evaluated, and three ideas using adhesive for the assembly were chosen for further studies and simulation. Existing products and machines were used in the designs when possible. By modeling and simulating the cells in simulation software, feasible cell designs was created, and cycle times were measured.The three proposed solutions all utilize an industrial robot, a vacuum gripper and adhesive as the assembly method. Two of the concepts has the robot attending different adhesive dispensing machines; one gantry and one conveyor. In the third concept, the robot applies the adhesive. The cell design that achieved the lowest cycle time in the simulations was the conveyor concept, with a cycle time of 21 seconds per sheet. The conclusion of the study is that investing in a robot cell would increase productivity. / Syftet med detta arbete var att designa en robotcell anpassad för tillverkning av värmeväxlarpaket i moduler. Målet var att besvara hur tillverkningen av värmeväxlare kan automatiseras samt vilken robot och övriga verktyg och maskiner som kan användas. Vidare skulle den möjliga produktionstakten och investeringskostnaden för designförslagen beräknas. Arbetet inleddes med en nulägesanalys och en litteraturstudie. Ett flertal experter och leverantörer inom automationsområdet konsulterades. Resultaten från detta låg till grund för en konceptgenereringsprocess i vilken ett flertal designidéer togs fram. Tre av dessa designförslag valdes ut för vidare studier och simulering. Genom att modellera och simulera robotcellerna kunde de utformas realistiskt och möjliga cykeltider beräknas. De tre designförslagen använder alla en robotarm, ett vakuumgripdon samt lim som metod för monteringen. Två av koncepten består av en medelstor robotarm som betjänar en limappliceringsmaskin. I ena konceptet är det en kartesisk robot med limbord som används för limappliceringen, i det andra är det ett transportband som för plastskivan under ett antal limpistoler. Det tredje designförslaget låter en större robot, utrustad med verktygsväxlare, utföra alla moment i processen genom att den byter verktyg mellan vakuumgripdon och limpistol. Det koncept som uppnådde den lägsta cykeltiden i simuleringarna var lösningen med rullbandet, med en cykeltid på 21 sekunder per skiva. Studiens slutsats är att en investering i en robotcell skulle leda till ökad produktivitet jämfört med manuell produktion.

The main task of this master thesis is design of robotic deburring workcell. The thesis informs about basic requests of object deburring using industrial robots. From layout variants, the one most suitable is picked. Chosen variant contains proper clamping solution as well as deburring tool and safety requirements. The concept design of robotic deburring cell in 3D visualization is the result of this diploma thesis.

Nuclear magnetic resonance (NMR) experiments are reported at up to 30.5 GPa of pressure using radiofrequency (RF) micro-coils with anvil cell designs. These are the highest pressures ever reported with NMR, and are made possible through an improved gasket design based on nano-crystalline powders embedded in epoxy resin. Cubic boron-nitride (c-BN), corundum (α-Al2O3), or diamond based composites have been tested, also in NMR experiments. These composite gaskets lose about 1/2 of their initial height up to 30.5 GPa, allowing for larger sample quantities and preventing damages to the RF micro-coils compared to precipitation hardened CuBe gaskets. It is shown that NMR shift and resolution are less affected by the composite gaskets as compared to the more magnetic CuBe. The sensitivity can be as high as at normal pressure. The new, inexpensive, and simple to engineer gaskets are thus superior for NMR experiments at high pressures.

A new design of a non-magnetic high-pressure anvil cell for nuclear magnetic resonance (NMR) experiments at Giga-Pascal pressures is presented, which uses a micro-coil inside the pressurized region for high-sensitivity NMR. The comparably small cell has a length of 22 mm and a diameter of 18 mm, so it can be used with most NMR magnets. The performance of the cell is demonstrated with externalforce vs. internal-pressure experiments, and the cell is shown to perform well at pressures up to 23.5 GPa using 800 μm 6H-SiC large cone Boehler-type anvils. 1H, 23Na, 27Al, 69Ga, and 71Ga NMR test measurements are presented, which show a resolution of better than 4.5 ppm, and an almost maximum possible signal-to-noise ratio.

An ever increasing demand for mobile broadband applications and services is leading to a massive network densification. The current cellular system architectures are both economically and ecologically limited to handle this. The concept of small-cell networks (SCNs) based on the idea of dense deployment of self-organizing; low-cost, low-power base station (BSs) is a promising alternative. Although SCNs have the potential to significantly increase the capacity and coverage of cellular networks while reducing their energy consumption, they pose many new challenges to the optimal system design. Due to small cell sizes, the mobile users cross over many cells during the course of their service resulting in frequent handovers. Also, due to proximity of BSs, users (especially those at cell edges) experience a higher degree of interference from neighboring BSs. If one has to derive advantages from SCNs, these alleviated effects have to be taken care either by compromising on some aspects of optimality (like dedicating extra resources) or by innovating smarter algorithms or by a combination of the two. The concept of umbrella cells is introduced to take care of frequent handovers. Here extra resources are dedicated to ensure that the calls are not dropped within an umbrella cell. To manage interference, one might have to ensure that the neighboring cells always operate in independent channels or design algorithms which work well in interference dominant scenarios or use the backhaul to incorporate BS cooperation techniques. Further, small cell BS are most often battery operated, which calls for efficient power utilization and energy conservation techniques. Also, when deployed in urban areas, some of the small cells can have larger concentration of users throughout the cell, for example, hot-spots, which call in for design of SCNs with dense users. Also, with portable BSs, one has the choice to install them on street infrastructure or within residential complexes. In such cases, cell design and resource allocation has to consider aspects like user density, distribution (indoor/outdoor), mobility, attenuation, etc. We present the thesis in two parts. In the first part we study the cell design aspects, while the second part deals with the resource allocation. While the focus is on SCNs, some of the results derived and the tools and techniques used are also applicable to conventional cellular systems.