Quality of Service (QoS) support for real-time traffic is a critical issue in high speed networks. The previously proposed Delay-Limiter Switch working with the Framed-Deadline Scheduler (FDS) is a combined input-output queuing (CIOQ) packet switch that can provide end-to-end bandwidth and delay guarantees for connection-oriented traffic. The Delay-Limiter Switch works with fixed-size packets. It has a scalable architecture and can provide QoS support for connection-oriented real-time traffic in a low-complexity fashion. The Delay-Limiter Switch serves connectionless traffic by using the remaining resources from the connection-oriented traffic. In this case, efficient management of the residual resources plays an important role on the performance of the connectionless traffic. This thesis work integrates new methods to the Delay-Limiter Switch that can improve the performance of the connectionless traffic while still serving the connection-oriented traffic with the promised QoS guarantees. A new method that makes it possible for the Delay-Limiter Switch to support variable-sized packets is also proposed.

The increasing use of the internet demands more powerful routers with higher speed, less power consumption and less physical space occupation. IP lookup operation is one of the major concerns in today&rsquo / s routers for providing such attributes. To accomplish IP lookup on routers, hardware or software based solutions can be used. In this thesis, an SRAM based pipelined architecture proposed earlier for ASIC implementation is re-designed and implemented on an FPGA in the form of a BRAM based pipelined 8x8 torus architecture using Xilinx ISE and simulated and verified using Modelsim Simulator. Some necessary modifications and improvements for FPGA implementation are carried out. The results of our experiments, which are performed for a real router lookup table and a real time traffic load with various optimizations, are also presented. Our study and design effort demonstrates the feasibility of the FPGA implementation of the proposed technique, of course with a considerable performance penalty.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第18989号 / 工博第4031号 / 新制||工||1621 / 31940 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 木本 恒暢, 教授 松尾 哲司 / 学位規則第4条第1項該当

We present fpga-ToPSS (Toronto Publish/ Subscribe System), an efficient FPGA-based middleware platform geared towards high-frequency and low-latency event processing. fpga-ToPSS is built over reconfigurable hardware---FPGAs---to achieve line-rate processing by exploiting unprecedented degrees of parallelism and potential for pipelining,only available through custom-built, application-specific and low-level logic design. Furthermore, our middleware solution hosts an event processing engine that is built on a hardware-based packet processor and Boolean expression matcher. Our middleware vision extends to a wide range of applications including real-time data analytics, intrusion detection, algorithmic trading, targeted advertisement, and (complex) event processing.

We present fpga-ToPSS (Toronto Publish/ Subscribe System), an efficient FPGA-based middleware platform geared towards high-frequency and low-latency event processing. fpga-ToPSS is built over reconfigurable hardware---FPGAs---to achieve line-rate processing by exploiting unprecedented degrees of parallelism and potential for pipelining,only available through custom-built, application-specific and low-level logic design. Furthermore, our middleware solution hosts an event processing engine that is built on a hardware-based packet processor and Boolean expression matcher. Our middleware vision extends to a wide range of applications including real-time data analytics, intrusion detection, algorithmic trading, targeted advertisement, and (complex) event processing.

Nowadays the popularity of WLANs is growing very rapidly. The basic solution for the connection of WLAN users to the global internet network is using leased lines or the other standard data transmission networks. But there may occur situations, when the only network for the data transmission we can use for the connection to the internet, is GSM network. In such a case, we are proposing to connect the users of WAN/WLAN networks by using GSM network, which has complete coverage in the territory of Lithuania. To guarantee the sufficient data transfer rate, we use bonding of several parallel GPRS/EDGE/UMTS channels into one total channel. In such a way we increase the reliability and data transfer rate of the total mobile data transmission channel. The parallel channels are bonded into one total channel by using either the hardware (Cisco) routers, or the software routers, configured using network administration tools of Linux operating system. In this work we give all the tools and configuration settings necessary for the realization of such a system. The results of QoS characteristics measurements are given too. We measure packet delay and data transfer rate. The majority of measurements are made by using several parallel GPRS channels because of wide spread GPRS technologies. The key accent of the system is free selection of the physical layer (OSI model) of the parallel channel. So we can bond either several GPRS, or EDGE, or UMTS channels.

“International Technology Roadmap for Semiconductors” (ITRS) teigia, kad baigiantis dešimtmečiui bus pagamintas 50 – 100 nm lustas susidedantis iš maždaug 4 bilijonų tranzistorių operuojančių 10Ghz. Taigi tokių parametrų sistemas pagaminti yra nelengva, tranzistorių skaičiaus didėjimas taip pat didina lusto dydį, lusto sud��tingumą bei sunkina lusto integruojamumą. Be to vienlustės sistemos naudoja bendras magistrales bendrauti su kitais lustiniais resursais. Šios magistralės yra nedalomos, todėl ateityje toks komunikavimo metodas taps vis didesne problema gaminant lustus susidedančius iš bilijonų tranzistorių. Šiems tikslams spręsti ir buvo pasiūlyta vienlusčių tinklo paradigma. Vienlusčių tinklų paradigma siūlo galimus komunikavimo infrastruktūrų sprendimus, susiduriant su vis sudėtingesnėmis sistemomis, bei padeda trumpinanti lusto pagaminimo laiko periodą. Šiame darbe naudojama atkartojimo technologijos, kuriant bendrini komponentą vienlusčių tinklams. Metaspecifikacija, sukurta naudojant preprocesorinį atkartojimo metodą. / According to the International Technology Roadmap for Semiconductors (ITRS), before the end of this decade we will be entering the era of a billion transistors on a single chip. It is being stated that soon we will have a chip of 50- 100 nm comprising around 4 billion transistors operating at a frequency of 10 Ghz. However, it has been observed that as the system grows, so does the complexity of integrating various components on a chip. The major threat toward the achievement of a billion transistor chip is poor scalability of current interconnect structure of today’s SoC. In order to cope with growing interconnect infrastructure, the “Network on chip (NoC)” concept was introduced. NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. It is clear that NoCs can potentially become the preferred interconnection approach for SoCs being developed in a near future. This paper discusses the impact of the reuse of NoC components methods, for parameterize and test these systems. There is preprocessing type reusing being used, to create a router metaspecification of router for the 2d torus interconnect network.

Network virtualization is becoming a fundamental building block of future Internet architectures. By adding networking resources into the “cloud”, it is possible for users to rent virtual routers from the underlying network infrastructure, connect them with virtual channels to form a virtual network, and tailor the virtual network (e.g., load application-specific networking protocols, libraries and software stacks on to the virtual routers) to carry out a specific task. In addition, network virtualization technology allows such special-purpose virtual networks to co-exist on the same set of network infrastructure without interfering with each other. Although the underlying network resources needed to support virtualized networks are rapidly becoming available, constructing a virtual network from the ground up and using the network is a challenging and labor-intensive task, one best left to experts. To tackle this problem, we introduce the concept of a HyperNet, a pre-built, pre-configured network package that a user can easily deploy or access a virtual network to carry out a specific task (e.g., multicast video conferencing). HyperNets package together the network topology configuration, software, and network services needed to create and deploy a custom virtual network. Users download HyperNets from HyperNet repositories and then “run” them on virtualized network infrastructure much like users download and run virtual appliances on a virtual machine. To support the HyperNet abstraction, we created a Network Hypervisor service that provides a set of APIs that can be called to create a virtual network with certain characteristics. To evaluate the HyperNet architecture, we implemented several example Hyper-Nets and ran them on our prototype implementation of the Network Hypervisor. Our experiments show that the Hypervisor API can be used to compose almost any special-purpose network – networks capable of carrying out functions that the current Internet does not provide. Moreover, the design of our HyperNet architecture is highly extensible, enabling developers to write high-level libraries (using the Network Hypervisor APIs) to achieve complicated tasks.

Designing hardware to output pixels for light field displays or multi-projector systems is challenging owing to the memory bandwidth and speed of the application. A new technique of hardware that implements ‗anywhere pixel routing‘ was designed earlier at the University of Kentucky. This technique uses hardware to route pixels from input to output based upon a Look up Table (LUT). The initial design suffered from high memory latency due to random accesses to the DDR SDRAM input buffer. This thesis presents a cache design that alleviates the memory latency issue by reducing the number of random SDRAM accesses. The cache is implemented in the block RAM of a field programmable gate array (FPGA). A number of simulations are conducted to find an efficient cache. It is found that the cache takes only a few kilobits, about 7% of the block RAM and on an average speeds up the memory accesses by 20-30%.

A low-cost power router (PR), capable of dynamic, independent control of active- and reactive-power flows on meshed grids is presented. The operating principle, detailed schematics, and various possible implementations of the proposed power router are discussed. Various operating modes are identified and a control algorithm has been proposed and verified through simulations. Small-signal and frequency-domain models of the power router from basic time-domain equations are developed. A three-tier protection system based on the fail-normal switch to avoid single point-of-failure is presented. The operation of proposed protection system in isolating the converter and the grid in the event of faults is verified through simulation. An analytical method to evaluate the stability of a system with multiple power routers is proposed. Necessary conditions for the PR-controller design to ensure stable operation of a system with multiple power routers is proposed. These necessary conditions are verified through simulation studies. Potential applications of proposed power router in distribution system and the associated challenges in implementation are presented. The functionality and advantages of the proposed power router are experimentally demonstrated at 13 kV, 1 MVA. The proposed power router can result in a low cost power routing solution that can reduce electric grid congestion and efficient implementation of RPS mandates.