Side-Channel Attacks (SCAs) have become a realistic threat to implementations of cryptographic algorithms. By utilizing the unintentionally leaked side-channel information during the execution of a cryptographic algorithm, it is possible to bypass the theoretical strength of the algorithm and extract its secret key. Recently, far-field electromagnetic (EM) emissions have been used in SCAs to extract keys from mixed- signal chips used in wireless communication protocols (such as Bluetooth). In such type of chips, the EM leakage is mixed with radio carrier and accidentally amplified by the antenna. Attacks exploiting such far-field EM side-channels may succeed over a much longer distance than the attacks based on near-field EM side-channels. Therefore, it is necessary to further investigate far-field EM side channels.In this thesis, we perform far-field EM side-channel attacks using two techniques: correlation and template analysis. We analyse an Arm Cortex-M4 microprocessor implementation of Advanced Encryption Standard (AES)-128 with a Bluetooth module on different distances up to 50cm. We first evaluate how the inter-chip diversity and the distance can affect the attack efficiency of template analysis. Our current results show that a template constructed using traces from one device captured at distance d can recover the secret key from 4,000 traces from the d device captured at the same distance d. However, if the distance is changed, or if traces are captured from different devices, the attack fails. This shows that it is not sufficient to build a template based on traces captured from a single device at a fixed distance. In addition, we present a pre- processing technique for allocating leakage points, which can significantly improve the attack efficiency of correlation analysis. / Side channel attacks har blivit ett realistiskt hot mot implementering av kryptografiska algoritmer. Genom att använda den oavsiktligt läckta sidokanalinformationen under exekveringen av en kryptografisk algoritm är det möjligt att kringgå algoritmens teoretiska styrka och extrahera dess hemliga nyckel. Nyligen har EM-utsläpp från fältfält använts i SCAsför att extrahera nycklar från blandade signalchips som används i trådlösa kommunikationsprotokoll (t.ex. Bluetooth). I en sådan typ av chips blandas EM-läckan med radiobäraren och förstärks av misstag av antennen. Attacker som utnyttjar sådana långtgående EM-sidokanaler kan lyckas på mycket längre avstånd än attackerna baserade på EM-sidokanaler nära fältet. Därför är det nödvändigt att ytterligare undersöka EM-sidokanalanalyser från fältet. I denna avhandling utför vi EM-sidokanalanalys med fältfält med två tekniker: korrelationsanalys och mallanalys. Vi analyserar en Arm Cortex-M4-mikroprocessorimplementering av AES med en Bluetooth-modul inbäddad på kortet på olika avstånd upp till 50 cm från den mottagande antennen. Vi utvärderar först hur mångfalden mellan chip och avståndet kan påverka attackeffektiviteten för mallanalys. Våra nuvarande resultat visar att en mall konstruerad med spår från en enhet fångad på avstånd d från den mottagande antennen kan återställa den hemliga nyckeln från 4K spår från samma enhet som fångats på samma avstånd d från den mottagande antennen. Om avståndet ändras eller om spår från en annan enhet analyseras misslyckas dock attacken. Detta visar att det inte är tillräckligt att bygga en mall baserad på spår från en enda enhet fångad på ett fast avstånd från den mottagande antennen. Dessutom presenterar vi en förbehandlingsteknik för allokering av läckagepunkter i spåren och visar att den kan förbättra attackeffektiviteten för korrelationsanalysen betydligt.

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In 2016, NIST started a post quantum cryptography (PQC) standardization project in response to the rapid development of quantum algorithms which break many public-key cryptographic schemes. As the project nears its end, it is necessary to assess the resistance of its finalists to side-channel attacks. Although several side-channel attacks on software implementations PQCfinalists have been presented in recent papers, hardware implementations have been investigated much less. In this thesis, we present the first side-channel attack on an FPGA implementation of one of the NIST PQC finalists, Saber. Our experiments are performed on a publicly availible implementation of Saber compiled with Xilinx Vivado for an Artix-7 XC7A100T FPGA. We trained several deep learning models in an attempt to recover the Hamming weight and value of messages using their corresponding power traces. We also proposed a method to determine the Hamming weight of messages through binary search based on these models. We found out that, due to the difference in software and hardware implementations, the previously presented message recovery method that breaks a masked software implementation of Saber cannot be directly applied to the hardware implementation. The main reason for this is that, in the hardware implementation used in our experiments, all 256 bits of a message are processed in parallel, while in the software implementation used in the previous work, the bits are processed one-by-one. Future works includes finding new methods for analyzing hardware implementations. / Under 2016 startade NIST ett standardiseringsprojekt efter kvantkryptering (PQC) som svar på den snabba utvecklingen av kvantalgoritmer som bryter många kryptografiska system med offentliga nyckel. När projektet närmar sig sitt slut är det nödvändigt att bedöma finalisternas motstånd mot sidokanalsattacker. Även om flera sidokanalsattacker på programvaruimplementationer PQC-finalister har presenterats i de senaste tidningarna, har hårdvaruimplementationer undersökts mycket mindre. I denna avhandling presenterar vi den första sidokanalsattacken på en FPGA-implementering av en av NIST PQC-finalisterna, Sabre. Våra experiment utförs på en allmänt tillgänglig implementering av Sabre kompilerad med Xilinx Vivado för en Artix-7 XC7A100T FPGA. Vi tränade f lera modeller för djupinlärning i ett försök att återställa Hamming-vikten och värdet av meddelanden med hjälp av deras motsvarande kraftspår. Vi föreslog också en metod för att bestämma Hamming-vikten för meddelanden genom binär sökning baserat på dessa modeller. Vi fick reda på att, på grund av skillnaden i mjukvaru- och hårdvaruimplementationer, kan den tidigare presenterade meddelandeåterställningsmetoden som bryter en maskerad mjukvaruimplementering av Sabre inte direkt appliceras på hårdvaruimplementeringen. Den främsta anledningen till detta är att i hårdvaruimplementeringen som används i våra experiment bearbetas alla 256 bitar i ett meddelande parallellt, medan i mjukvaruimplementeringen som användes i det tidigare arbetet bearbetas bitarna en i taget. Framtida arbete inkluderar att hitta nya metoder för att analysera hårdvaruimplementationer.

Electronic devices such as phones and computers use cryptography to achieve information security. However, while cryptographic algorithms may be strong theoretically, their physical implementations in hardware can leak unintentional side information as a byproduct of performing their computations. A device's security can be compromised from this leakage through side-channel attacks. Research in hardware security reveals how dangerous these attacks can be and provides security countermeasures. This thesis focuses on a category of side-channel attacks called fault attacks, and contributes a new fault attack method that can compromise a cryptographic device more rapidly than the previous methods when using practical fault injection techniques. We observe that as a circuit is further overclocked, new faults are often superimposed upon previous ones. We analyze the incremental changes rather than the total sum in order to extract more secret information. Unlike many previous methods, ours does not require precise fault injection techniques and requires no knowledge of when the internal state is in a specific algorithmic stage. Results are confirmed experimentally on hardware implementations of AES-128, 192, and 256. / Thesis / Master of Applied Science (MASc)

Globalization in semiconductor industry has surged up the trend of outsourcing component design and manufacturing process across geographical boundaries. While cost reduction and short time to market are the driving factors behind this trend, the authenticity of the final product remains a major question. Third party deliverables are solely based on mutual trust and any manufacturer with a malicious intent can fiddle with the original design to make it work otherwise than expected in certain specific situations. In case such a backfire happens, the consequences can be disastrous especially for mission critical systems such as space-explorations, defense equipments such as missiles, life saving equipments such as medical gadgets where a single failure can translate to a loss of lives or millions of dollars. Thus accompanied with outsourcing, comes the question of trustworthy design - "how to ensure that integrity of the product manufactured by a third party has not been compromised". This dissertation aims towards developing verification methodologies and implementing non-destructive testing strategies to ensure the authenticity of a third party IP. This can be accomplished at various levels in the IC product life cycle. At the design stage, special testability features can be incorporated in the circuit to enhance its overall testability thereby making the otherwise hard to test portions of the design testable at the post silicon stage. We propose two different approaches to enhance the testability of the overall circuit. The first allows improved at-speed testing for the design while the second aims to exaggerate the effect of unwanted tampering (if present) on the IC. At the verification level, techniques like sequential equivalence checking can be employed to compare the third-party IP against a genuine specification and filter out components showing any deviation from the intended behavior. At the post silicon stage power discrepancies beyond a certain threshold between two otherwise identical ICs can indicate the presence of a malicious insertion in one of them. We have addressed all of them in this dissertation and suggested techniques that can be employed at each stage. Our experiments show promising results for detecting such alterations/insertions in the original design. / Ph. D.