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A systematic method was developed for the deposition of β-SiC thin films on Si(100) substrates in a hot wall reactor, using low pressure chemical vapor deposition (LPCVD). Due to poor adhesion resulting from lattice mismatch and difference in thermal expansion coefficients between the (SiC films and the Si(100) substrates, the feasibility of forming a SiC buffer layer on the Si(100) surface before beginning the chemical vapor deposition (CVD) process was investigated. The SiC buffer layers were formed with either a smooth or porous morphology. A nonporous Si(100) substrate with a 35Å thick SiC buffer layer was formed when the Si surface was heated at 1050°C in an atmosphere of C₂H₂ and H₂. A porous surface was obtained when the Si substrate was heated at 1000°C in C₂H₂ alone. The porous defects were correlated to the out—diffusion of Si in the carburizing process. On smooth Si(100) substrates, polycrystalline and stoichiometric β-SiC thin films with the (111) planes paralleling the Si(100) substrates were grown from a CH₃SiCl₃ (MTS)—H₂ mixture at 1050°C. At high H₂/MTS ratios and/or low deposition pressures, no etching on the Si substrates of the β-SiC films was observed, resulting in a smooth topography. Degradation in film morphology, changes in the preferred orientation, and etching of the Si substrates were observed at higher pressures, temperatures, and H₂/MTS ratios. The etching of the Si substrate was due to the out—diffusion of Si atoms from the substrate and the presence of Cl—containing radicals, which resulted from the decomposition of MTS molecules before arriving at the substrates. A model of the deposition mechanism is proposed which predicts the deposition rates in a hot wall CVD reactor and agrees very well with the experimental data. On the Si(100) substrate with a porous topography, epitaxial β-SiC(100) thin films were grown from MTS—H₂ at 1150°C. The crystallinity of the deposited films was influenced by the deposition time. With increasing deposition time, rotational β-SiC(100) crystals and polycrystalline β-SiC with a highly preferred orientation of (100) and/or (111) were obtained. At a lower temperature of 1100°C, poor morphology and polycrystalline β-SiC thin films were observed. Finally, a new approach to the calculation of the local equilibrium CVD phase diagrams, which represent the most stable phases above the substrates in a hot wall reactor, for SiC deposition from the MTS—H₂ gas mixture by coupling the depletion effects to the equilibrium thermodynamic computer code SOLGASMIX—PV. The calculated CVD phase diagrams were also compared with experimental and the literature data. Although the local equilibrium CVD phase diagrams predicted the deposition of single phase SiC better than established CVD phase diagrams, the experimental regions for depositing single phase SiC are larger than those calculated from local CVD phase diagrams. This may be because of the high linear velocity of the gas flux under low pressure and the polarity of the Si—containing intermediate species. / Ph. D.

SiC whisker reinforced (Ca_0.6,Mg_0.4)Zr₄(PO₄)₆ (CMZP) matrix composites containing 10, 20, and 30 vol % whiskers were produced using a glass encapsulated hot isostatic pressing (HIPing) technique. The best HIPing temperature, pressure, and time conditions to optimize composite density and strength were determined to be 1050°C, 103 MPa, and 0.25 h. / Ph. D.

Galvanic isolation between the grid and energy storage unit is typically required for bidirectional power distribution systems. Due to the recent advancement in wide-bandgap semiconductor devices, it has become feasible to achieve the galvanic isolation using bidirectional isolated DC/DC converters instead of line-frequency transformers. A survey of the latest generation SiC MOSFET is performed. The devices were compared against each other based on their key parameters. It was determined that under the given specifications, the most suitable devices are X3M0016120K 1.2 kV 16 mohm and C3M0010090K 900 V 10 mohm SiC MOSFETs from Wolfspeed. Two of the most commonly utilized bidirectional isolated DC/DC converter topologies, dual active bridge and CLLC resonant converter are introduced. The operating principle of these converter topologies are explained. A comparative analysis between the two converter topologies, focusing on total device loss, has been performed. It was found that the CLLC converter has lower total device loss compared to the dual active bridge converter under the given specifications. Loss analysis for the isolation transformer in the CLLC resonant converter was also performed at different switching frequencies. It was determined that the total converter loss was lowest at a switching frequency of 250 kHz A prototype for the CLLC resonant converter switching at 250 kHz was then designed and built. Bidirectional power delivery for the converter was verified for power levels up to 25 kW. The converter waveforms and efficiency data were captured at different power levels. Under forward mode operation, a peak efficiency of 98.3% at 15 kW was recorded, along with a full load efficiency value of 98.1% at 25 kW. Under reverse mode operation, a peak efficiency of 98.8% was measured at 17.8 kW. The full load efficiency at 25 kW under reverse mode operation is 98.5%. / Master of Science

A novel material, (Ca_0.6,Mg_0.4)Zr₄(PO₄)₆ (CMZP), was evaluated as a weak interface coating for SiC/SiC composites. A procedure was developed to put down uniform and crack-free CMZP coatings on Nicalon cloth and tows using sol-gel and metal organic deposition (MOD). The coated Nicalon cloth samples and tows were infiltrated with SiC matrix using Chemical Vapor Infiltration (CVI). Bars were cut for flexure testing from the infiltrated composite containing Nicalon cloth samples that had been coated using sol-gel. These composites failed gracefully, 1.e., there was fiber pullout and debonding probably at the matrix-coating interface. Minicomposites that contained tows coated using MOD were too weak to be tested for tensile strength. This necessitated the deposition of a thin (~ 30 nm) layer of carbon both on the tows before depositing CMZP coating to protect the fibers as well as on the CMZP coating to protect the coating. Minicomposites that contained these tows, coated using sol-gel and MOD, demonstrated extensive pullout and debonding. The composite behavior could not have been due to the carbon alone as there was very less (~ 60-80 nm) present. Thus, the CMZP coating was responsible, probably in addition to the carbon layers, for the composite behavior. / Master of Science

Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density. / Ph. D. / Electricity is the fastest-growing type of end-use energy consumption in the world, and its generation and usage trends are changing. Hence, the power electronics that control the flow and conversion of electrical energy are an important research area. Advanced power electronics with improved efficiency, power density, reliability, and functionality are critical in data center, transportation, motor drive, renewable energy, and grid applications, among others. Wide-bandgap power semiconductors are enabling power electronics to meet these growing demands, and have thus begun appearing in commercial products, such as traction and solar inverters. Looking ahead, even greater strides can be made in medium-voltage systems due to the development of silicon carbide power devices with voltage ratings exceeding 10 kV. The ability of these devices to switch higher voltages faster and with lower losses than existing semiconductor technologies will drastically reduce the size, weight, and complexity of medium-voltage systems. However, these devices also bring new challenges for designers. This dissertation will present a package for 10 kV silicon carbide power MOSFETs that addresses the enhanced electric fields, greater electromagnetic interference, worsened dynamic imbalance, and higher heat flux issues associated with the packaging of these unique devices. Specifically, due to the low and balanced parasitic inductances, the power module prototype is able to switch at record speeds of tens of nanoseconds with negligible ringing and voltage overshoot. An integrated common-mode current screen contains the current that is generated by these fast voltage transients within the power module, rather than flowing to the system ground. This screen connection simultaneously increases the partial discharge inception voltage by reducing the electric field strength at the triple point of the insulating ceramic substrate. Further, field-grading plates are used in the bus bar to reduce the electric field strength at the module terminations. The heat flux is addressed by employing direct-substrate, jet-impingement cooling. The cooler is integrated into the module housing for increased power density.

There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0–40V) and high voltage (40–5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed. / Master of Science

Graphene is widely considered to be a promising candidate for a new generation of electronics, but there are many outstanding fundamental issues that need to be addressed before this promise can be realized. This thesis focuses on the production and properties of graphene grown epitaxially on the carbon terminated face (C-face) of hexagonal silicon carbide leading to the construction of a novel graphene transistor structure. C-face epitaxial graphene multilayers are unique due to their rotational stacking that causes the individual layers to be electronically decoupled from each other. Well-formed C-face epitaxial graphene single layers have exceptionally high mobilities (exceeding 10,000 cm ²/Vs), which are significantly greater than those of Si-face graphene monolayers. This thesis investigates the growth and properties of C-face single layer graphene. A field effect transistor based on single layer graphene was fabricated and characterized for the first time. Aluminum oxide or boron nitride was used for the gate dielectric. Additionally, an all graphene/SiC Schottky barrier transistor on the C-face of SiC composed of 2DEG in SiC/Si₂O ₃ interface and multilayer graphene contacts was demonstrated. A multiple growth scheme was adopted to achieve this unique structure.