O carbeto de silício (SiC) é um material que apresenta baixa expansão térmica, altas resistências mecânica e ao choque térmico e alta condutividade térmica. Em razão disto é empregado na confecção de mobília de fornos de sinterização. O SiC no entanto sofre degradação a altas temperaturas quando submetido a atmosferas agressivas. A utilização de recobrimentos protetores evita a exposição direta da superfície do material à atmosfera dos fornos; a mulita pode ser um recobrimento protetor apropriado em razão de sua alta estabilidade em temperaturas elevadas e seu coeficiente de expansão térmica compatível com o do SiC (4x10-6/°C e 5,3x10-6/°C, respectivamente). No presente trabalho foi estudada a obtenção de recobrimento de mulita, para refratário de SiC, a partir da utilização de polímero precursor cerâmico e alumínio particulado. Foram preparadas composições com 10, 20, 30 e 50% (vol.) de alumínio adicionado ao polímero, sendo utilizados pós de alumínio de diferentes distribuições de tamanhos de partículas. As composições foram submetidas a diversos ciclos térmicos para determinação da condição mais adequada à obtenção de alto teor de mulita. A composição que apresentou melhor resultado foi a contendo 20% do pó de Al de menor tamanho de partículas. A partir desta, foi preparada e aplicada suspensão para ser aplicada sobre o refratário de SiC. A suspensão aplicada, após seca, reticulada e tratada termicamente a 1580°C, originou um recobrimento de mulita. Foram realizados ciclos de choque térmico em amostras com e sem recobrimento para comparação, num total de 26 ciclos. As condições foram 600°C/30 min. seguida de resfriamento ao ar até a temperatura ambiente. Após cada choque térmico, as amostras foram caracterizadas por microscopia óptica e eletrônica e determinado o módulo de elasticidade. Os recobrimentos apresentaram boa adesão e não foram detectados danos significativos após os choques térmicos. / Silicon carbide (SiC) presents low thermal expansion, high strength and thermal conductivity. For this reason it is used as kiln furniture for materials sintering. On the other hand, SiC degrades at high temperature under aggressive atmosphere. The use of protective coatings can avoid the right exposition of SiC surface to the furnace atmosphere. Mullite can be a suitable material as protective coating because of its high corrosion resistance and thermal expansion coefficient matching that of SiC (4,7 x10-6/°C e 5,3 x10-6/°C, respectively). In the present work a mullite coating obtained from ceramic precursor polymer and aluminium powder was studied to be applied over SiC refractories. Compositions were prepared with 10, 20, 30 and 50% (vol.) of aluminium powder added to the polymer. They were used aluminium powders with different distributions sizes These compositions were heat treated at different thermal cycles to determine a suitable condition to obtain a high mullite content. The composition with 20% of the smaller particle size Al powder was selected and used to be applied as a suspension over SiC refractory. The applied suspension, after dried, crosslinked and heat treated, formed a mullite coating over SiC refractory. Cycles of thermal shock were performed in coated and uncoated SiC samples to compare each other. They were carried out 26 cycles of thermal shock, in the following conditions: 600°C/30 min. and air cooling to room temperature. After each thermal shock, samples were analised by mean of optical and electron microscopy, elastic modulus was also determined. After thermal shock cycles the coating presented good adhesion and no significant damage were observed.

A tecnologia dos semicondutores tem exigido materiais alternativos para substituir a silício em aplicações a altas temperaturas, altas potências e altas frequências. O carbeto de silício (SiC) emergiu como um dos sérios candidatos que poderiam operar sob extremas condições. O carbeto de silício é um semicondutor que apresenta uma grande faixa proibida de energia e possui mais de 200 politipos. Dentre esses politipos, a maioria das pesquisas tem sido focada nos politipos hexagonais (4H e 6H) e cúbico (3C). Com o objetivo de desenvolver novos dispositivos baseados em SiC, é importante obter um controle bastante rígido sobre os defeitos nativos e as impurezas no material. Os metais de transição tais como titânio, vanádio e cromo são impurezas residuais comuns que são incorporadas durante o crescimento e podem afetar as propriedades eletrônicas do material. Vanádio e cromo são conhecidos como geradores de centros eletricamente ativos em todos os politipos até agora investigados. Por outro lado , a atividade elétrica das impurezas de titânio dependem do politipo de SiC. Apesar do grande interesse que as impurezas de metais de transição despertam devido a suas aplicações tecnológicas associadas a produção de dispositivos eletrônicos, estudos teóricos, utilizando métodos de energia total, têm sido limitados devido a complexidade destes sistemas. Neste trabalho, realizamos uma investigação teórica das principais propriedades eletrônicas e estruturais das impurezas de Ti, V e Cr nos politipos 3C e 2H de SiC em vários estados de carga. O método utilizado é o FP-LAPW (Full Potential Linearized Augmented Plane Wave), que é baseado na teoria do funcional da densidade, dentro da aproximação da supercélula. As geometrias e estruturas atômicas de Ti, V e Cr assim como suas estabilidades são investigadas. Para cada configuração, os átomos ao redor do sítio da impureza são relaxados de acordo com o esquema de Newton. ) Este é o primeiro estudo de propriedades eletrônicas e estruturais de impurezas de metais de transição em um material semicondutor, dentro de um formalismo de primeiros princípios, onde distorções da rede cristalina são consideradas. Nossos resultados são comparados com os dados experimentais disponíveis na literatura. / Current semiconductor techonology has required alternative materials to silicone, for applications at high temperatures, high powers, and high frequencies. Silicon carbide (SiC) has emerged as one of the leading candidates which could be operated under such extreme conditions. Silicon carbide is a wide band gap semiconductor which has more than 200 know polytypes. From all those polytypes, research has been focused on hexagonal (4H and 6H) and cubic (3C) SiC. In order to develop SiC-based new devices, it is important to achieve a strict control over native defects and impurities in the material. Transitions metals, such as titanium, vanadium, and chromium, are commum residual impurities which are incorporated during growth, and they may affect the electronic properties of the material. Vanadium and chromium are known to generated electrically active centers in all so far investigated SiC polytypes. On the other hand, the electrical activity of titanium impurities depends on the host SiC polytype. Although transition metal impurities in semiconductors have attracted a great deal of interest due to their technological applications in device production, the theoretical studies using total-energy methods have been limited because of the complexity of the systems. In this work we carried a theoretical investigation of the main electronic and structural properties of Ti, V and Cr impurities in 3C and 2H SiC in the neutral and charged states of the impurities. As a method we have used the FPLAPW (Full Potential Linearized Augmented Plane Wave Method) in the supercell approach. The geometries and atomic structures, transitions and formation energies of isolated impurities of Ti, V and Cr were investigated as well their stabilities. For each configuration, the atoms around the impurity site are allowed to relax without any constrains, following the damped Newton scheme. Our results are compared to available experimental data on literature.

In the most recent two decades, the development of impurity controls with ultra-high precision in semiconductors motivates people to put more and more attentions on the solotronic devices, whose properties depend on one or a few dopants. One of the most promising applications of solotronic device is the qubit in quantum computing. In the procedure of exploring qubit candidates, the most straightforward challenges we need face include that the qubit must be highly isolated and can be initialized/manipulated efficiently with high fidelities. It has been proved that qubits based on single defects have excellent performances as quits. For instance, the NV center in diamond forms a ground spin triplet which can be manipulated at room temperature with electromagnetic fields. This work focuses on searching for new single defects as qubit candidates with density functional theory. Lanthanides element possesses excellent optical characteristics and extremely long nuclear coherence time. Therefore, combining it into the diamond platform can be possible design for integrated quantum information processing devices in the future. To investigate the stability of lanthanides dopants in the diamond matrix, the formation energies of charge states of complexes are calculated. The broadening of Eu(III) peak in the photoluminescence spectrum can be verified according to the existence of more than stable configuration and steady 4f electron occupation. In the case of transition-metal dopant in the silicon carbide, it is found that both silicon and carbon substituted nickels in 3C-SiC shows a magnetic-antimagnetic transition under applied strains. The virtual hopping rate of electrons strongly depends on the distance between the spin pair residing in the nickel and dangling bonds. Therefore, the Heisenberg exchange coupling between them can be adjusted subtly by controlling the external strain. According to the the spin Hamiltonian of the defect, the spin state can be manipulated universally with strain and electromagnetic fields. In contrast, the nickel dopant in 4H-SiC exhibits a very stable magnetic property. Other than that, the electronic structure of Cr in 4H-SiC implies that optical manipulations of spin states might be realized in the excited state.

The goal of this research is to develop a post-implantation annealing process in silicon carbide (SiC). Due to the low diffusivities of dopants in SiC, even at temperatures in excess of 2000°C, diffusion is not a suitable process to achieve selective, planar doping. Ion implantation is therefore the most suitable means for achieving selective doping in SiC crystals. The strong covalent bonding in SiC requires that selective doping be performed via high-energy ion implantation. As a consequence of the high ion energy and flux, there is considerable lattice damage to the crystal surface. To repair the damage caused by the implantation, as well as to electrically activate the dopants, it is important to perform post-implantation thermal annealing at temperatures greater than 1600°C. However annealing at such high temperatures decomposes the SiC crystal surface due to the selective out-diffusion of Si causing surface morphology degradation. In this research two processes, both using a silane-based SiC CVD reactor, have been realized to minimize the evaporation of Si. This is accomplished by providing Si overpressure above the wafer surface during annealing thus suppressing the evaporation of Si from the lattice. Post-implantation anneals were performed in both hot-wall and cold-wall silane-based chemical vapor deposition (CVD) reactors. For each process temperature developed, silane was added to a stream of Ar in such a concentration such that the suppression of step-bunching, a well known phenomenon caused by the evaporation of Si at the surface, was achieved. The surfaces were studied after annealing via plan-view secondary electron microscopy (SEM) and atomic force microscopy (AFM). The resulting surface morphology was found to be both step-free and smooth. Results of the annealing process developed, the surface characterization performed and electrical data relating to the dopant activation and implanted region conductivity are presented.

Silicon carbide (SiC) is a wide band-gap semiconductor with advantageous electrical and thermal properties making it attractive for high temperature and power applications. However, difficulties with oxide/SiC structures have posed challenges to the development of practical MOS-type devices. Surface conditioning and oxidation of 4H-SiC were investigated using a novel sequential afterglow processing approach combined with the unique capabilities of non-contact corona-Kelvin metrology. The use of remote plasma assisted thermal oxidation facilitated film growth at low temperature and pressure with the flexibility of sequential in-situ processing options including pre-oxidation surface conditioning. Corona-Kelvin metrology (C-KM) provided a fast, non-destructive method for electrical evaluation of oxide films and semiconductor surfaces. Non-contact C-KM oxide capacitance-voltage characteristics combined with direct measurement of SiC surfaces using C-KM depletion surface barrier monitoring and XPS analysis of surface chemistry were interpreted relating the impact of afterglow conditioning on the surface and its influence on subsequent oxide thin film growth. Afterglow oxide films of thicknesses 50-500 angstroms were fabricated on SiC epi-layers at low growth temperatures in the range 600-850°C, an achievement not possible using conventional atmospheric oxidation techniques. The inclusion of pre-oxidation surface conditioning in forming gas (N2:H2)* afterglow was found to produce an increase in oxide growth rate (10-25%) and a significant improvement in oxide film thickness uniformity. Analysis of depletion voltage transients on conditioned SiC surfaces revealed the highest degree of surface passivation, uniformity, and elimination of sources of charge compensation accomplished by the (N2:H2)* afterglow treatment for 20 min. at 600-700°C compared to other conditioning variations. The state of surface passivation was determined to be very stable and resilient when exposed to a variety of temporal, electrical, and thermal stresses. Surface chemistry analysis by XPS gave evidence of nitrogen incorporation and a reduction of the C/Si ratio achieved by the (N2:H2)* afterglow surface treatment, which was tied to the improvements in passivation, uniformity, and growth rate observed by non-contact C-KM measurements. Collective results were used to suggest a clean, uniform, passivated, Si-enriched surface created by afterglow conditioning of 4H-SiC as a sequential preparation step for subsequent oxidation or dielectric formation processing.

No description available.

This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.

<p>SiC is an attractive material since it has remarkable properties. For several years efforts have been put primarily in electronic applications. High power and high frequency devices can be fabricated on SiC due to its wide band gap, high breakdown field and high thermal conductivity. SiC devices can be used in harsh environment since its operation temperature is significantly high (about 1200 ). SiC bulk growth has been improved by seeded physical vapour transport (PVT) during last decades. However, the quality and doping concentration of SiC bulk are not good enough to be used as an active layer for devices. SiC epilayer growth by chemical vapour deposition (CVD) was established in the last three decades. Only about 5 µm/h growth rate is achieved by CVD with a standard process. Long deposition time is required to grow ≥100µm thick epilayer for high voltage devices. The main problem in standard CVD is the formation of silicon (Si) droplets due to supersaturation of Si-species on the growth surface or in the gas-phase, which is detrimental for devices performance. To solve the problem of Si-droplets, chloride-based CVD was introduced. Chlorinated species can dissolve the silicon aggregates through the formation of strong bonds to silicon species compared to Si-Si bonds. Typical chlorinated precursors are hydrogen chloride (HCl) and methyltrichlorosilane (MTS). In this thesis study, HCl was mainly used as chlorinated precursors. Distinct chlorinated precursors result in different chemical reactions which affect the epilayer growth appreciably. The Cl/Si ratio, which is the ratio of the amount of chlorinated precursors to silicon precursors, is a very critical growth parameter for morphology, growth rate and background doping concentration. The C/Si ratio and Si/H₂ ratio also affect the epilayer growth appreciably. Besides, growth temperature, growth pressure and temperature ramp up condition are other important growth parameters. In the CVD reaction chamber, the temperature profile and gas species distribution are not uniform along the whole susceptor length, which leads to different thickness of epilayer, morphology and doping concentration at different area of the reaction chamber. The polarity and off-angle of substrates can bring about complete different grown epilayers. Epitaxial defects are mainly replicated from the substrate. Therefore, the quality of substrates is very important as well. Deep energy levels can be introduced by adding transition metal such as vanadium (V), chromium (Cr) or tungsten (W). There are some limits which are needed to be overcome for a complete development of SiC. 4” SiC wafers are commercially available on the market, larger diameter would be very useful for the industrial development of SiC. High growth rate and good quality with controlled uniformity are desired for electronic applications. In this thesis, the influences of growth parameters such as C/Si and Cl/Si ratios, comparison between different precursors, growth condition in different areas of reaction chamber and effects of substrate polarity are discussed. Intentional incorporation of tungsten atoms is investigated by deep-level transient spectroscopy measurement and thermodynamic analysis.</p>

MEMS-based gas turbine engines are currently under development at MIT for use as a button-sized portable power generator or micro-aircraft propulsion sources. Power densities expected for the micro-engines require very high rotor peripheral speeds of 300-600m/s and high combustion gas temperatures of 1300-1700K. These harsh requirements for the engine operation induce very high stress levels in the engine structure, and thus call for qualified refractory materials with high strength. Silicon carbide (SiC) has been chosen as the most promising material for use due to its high strength and chemical inertness at elevated temperatures. However, the state-of-the art microfabrication techniques for single-crystal SiC are not yet mature enough to achieve the required level of high precision of micro-engine components. To circumvent this limitation and to take advantage of the well-established precise silicon microfabrication technologies, silicon-silicon carbide hybrid turbine structures are being developed using chemical vapor deposition (CVD) of thick SiC (up to ~70µm) on silicon wafers and wafer bonding processes. Residual stress control of thick SiC layers is of critical importance to all the silicon-silicon carbide hybrid structure fabrication steps since a high level of residual stresses causes wafer cracking during the planarization, as well as excessive wafer bow, which is detrimental to the subsequent planarization and bonding processes. The origins of the residual stress in CVD SiC layers have been studied. SiC layers (as thick as 30µm) with low residual stresses (on the order of several tens of MPa) have been produced by controlling CVD process parameters such as temperature and gas ratio. Wafer-level SiC planarization has been accomplished by mechanical polishing using diamond grit and bonding processes are currently under development using CVD silicon dioxide as an interlayer material. This paper reports on the work that has been done so far under the MIT micro-engine project. / Singapore-MIT Alliance (SMA)

Electronic components, based on current semiconductor technologies and operating in radiation rich environments, suffer degradation of their performance as a result of radiation exposure. Silicon carbide (SiC) provides an alternate solution as a radiation hard material, because of its wide bandgap and higher atomic displacement energies, for devices intended for radiation environment applications. However, the radiation tolerance and reliability of SiC-based devices needs to be understood by testing devices  under controlled radiation environments. These kinds of studies have been previously performed on diodes and MESFETs, but multilayer devices such as bipolar junction transistors (BJT) have not yet been studied. In this thesis, SiC material, BJTs fabricated from SiC, and various dielectrics for SiC passivation are studied by exposure to high energy ion beams with selected energies and fluences. The studies reveal that the implantation induced crystal damage in SiC material can be partly recovered at relatively low temperatures, for damag elevels much lower than needed for amorphization. The implantation experiments performed on BJTs in the bulk of devices show that the degradation in deviceperformance produced by low dose ion implantations can be recovered at 420 oC, however, higher doses produce more resistant damage. Ion induced damage at the interface of passivation layer and SiC in BJT has also been examined in this thesis. It is found that damaging of the interface by ionizing radiation reduces the current gain as well. However, for this type of damage, annealing at low temperatures further reduces the gain. Silicon dioxide (SiO2) is today the dielectric material most often used for gate dielectric or passivation layers, also for SiC. However, in this thesis several alternate passivation materials are investigated, such as, AlN, Al2O3 and Ta2O5. These materials are deposited by atomic layer deposition (ALD) both as single layers and in stacks, combining several different layers. Al2O3 is further investigated with respect to thermalstability and radiation hardness. It is observed that high temperature treatment of Al2O3 can substantially improve the performance of the dielectric film. A radiation hardness study furthermore reveals that Al2O3 is more resistant to ionizing radiation than currently used SiO2 and it is a suitable candidate for devices in radiation rich applications. / QC 20120117