Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test.

Zugl.: Hamburg, Universiẗat, Diss., 2009.

<p>This paper is concerned with the newly reformed national English test for Chinese college students, called the College English Test (CET) Band 4 (or Level 4). By comparing the test before and after it was reformed, there will be a close examination with regard to the aspects of test reliability, construct validity, authenticity, interactiveness, impact and practicality. With an extra focus on how vocabulary and grammar are tested, the paper aims to investigate the extent to which the new system is considered useful and how effective it is in testing vocabulary and grammar.</p>

This paper is concerned with the newly reformed national English test for Chinese college students, called the College English Test (CET) Band 4 (or Level 4). By comparing the test before and after it was reformed, there will be a close examination with regard to the aspects of test reliability, construct validity, authenticity, interactiveness, impact and practicality. With an extra focus on how vocabulary and grammar are tested, the paper aims to investigate the extent to which the new system is considered useful and how effective it is in testing vocabulary and grammar.

The production testing cost of modern wireless communication systems, especially basestation units, is estimated to be as high as 30-40 percent of their manufacturing cost and is increasing with system complexity, high levels of device integration and scaling of CMOS process technology and operating frequencies. The major production testing challenges for RF transceivers are: (a) the high cost of automated test development because of system-level simulation difficulties and the large simulation times involved, (b) the high cost of using high-end, communication protocol-aware RF test instrumentation, and (c) lack of external test access to RF circuits embedded inside integrated transceivers. Consequently, there exists a need for developing efficient design-for-test methodologies and non-invasive system-level test techniques for wireless transceivers to reduce their test cost. This dissertation is focused towards development of new system-level alternate test methodologies for RF transceiver architectures. The research proposes using non-invasive testing techniques for RF subsystems and digital-compatible built-in testing techniques for baseband and intermediate frequency (IF) analog circuits. The objectives of this research are: (a) to develop automatic test stimulus generation algorithms that allow accurate determination of targeted RF system-level test specification values using behavioral modeling and simulation techniques, (b) to develop RF transceiver test techniques that allow testing of embedded RF systems with limited test access, while reducing the test time for complex RF and baseband system-level performance metrics (b) to significantly reduce the test instrumentation overhead for testing complex frequency-domain and modulation-domain system specifications. The feasibility and the cost benefits of using the proposed alternate test approaches have been demonstrated using 900 MHz and 1575 MHz transceiver prototypes.

Testing is the dominating method for quality assurance of industrial software. Despite its importance and the vast amount of resources invested, there are surprisingly limited efforts spent on testing research, and the few industrially applicable results that emerge are rarely adopted by industry. At the same time, the software industry is in dire need of better support for testing its software within the limited time available. Our aim is to provide a better understanding of how test cases are created and applied, and what factors really impact the quality of the actual test. The plethora of test design techniques (TDTs) available makes decisions on how to test a difficult choice. Which techniques should be chosen and where in the software should they be applied? Are there any particular benefits of using a specific TDT? Which techniques are effective? Which can you automate? What is the most beneficial way to do a systematic test of a system? This thesis attempts to answer some of these questions by providing a set of guidelines for test design, including concrete suggestions for how to improve testing of industrial software systems, thereby contributing to an improved overall system quality. The guidelines are based on ten studies on the understanding and use of TDTs. The studies have been performed in a variety of system domains and consider several different aspects of software test. For example, we have investigated some of the common mistakes in creating test cases that can lead to poor and costly testing. We have also compared the effectiveness of different TDTs for different types of systems. One of the key factors for these comparisons is a profound understanding of faults and their propagation in different systems. Furthermore, we introduce a taxonomy for TDTs based on their effectiveness (fault finding ability), efficiency (fault finding rate), and applicability. Our goal is to provide an improved basis for making well-founded decisions regarding software testing, together with a better understanding of the complex process of test design and test case writing. Our guidelines are expected to lead to improvements in testing of complex industrial software, as well as to higher product quality and shorter time to market.

Abstract Under the great impact and known to all, the structural changes may be obviously clear that can be observed out, when being not so obvious, should observe whether there are structural changes to appear, it is very difficult to get a clear result clearly to turn into. This paper tries to use such models as Chow test, CUSUM test, CUSUMSQ test, STAR in unknown cases, whether going to assay the data separately has structural changes, various kinds of examination ways of result received are each different to some extent, clear conclusion not unanimous and unified. The dominance the Chow test is the most obvious; Consider heteroscedasticity and autocorrelation restriction in because CUSUM test and CUSUMSQ test model, it is not apt to demonstrate the dominance instead; The STAR depends on state of the materials.

Made available in DSpace on 2014-06-12T15:52:41Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / A busca por novas funcionalidades no que diz respeito a melhoria da confiabilidade dos sistemas eletrônicos e também a necessidade de gerir o tempo gasto durante o teste faz do mecanismo Built-in-Self-Test (BIST) um característica promissora a ser integrada no fluxo atual de desenvolvimento de Circuitos Integrados (IC). Existem vários tipos de BIST: Memories BIST, Logical BIST (LBIST) e também alguns mecanismos usados para teste as partes analógicas do circuito. O LBIST tradicional usa um hardware on-chip para gerar todos os padrões de teste com um gerador pseudo aleatório (PRPG) e analisa a assinatura de saída gerada por um registrador de assinatura de múltipla entradas (MISR). Essa abordagem requer a inserção de pontos de teste extras or armazenagem de informação fora do chip que tornará possível alcançar uma cobertura de teste > 98%. Também a geração de todos os estímulos de teste implica no sacrifício no tempo aplicação do teste, o qual pode ser aceitável para pequenos sistemas executarem auto-teste durante a inicialização do sistema mas pode tornasse um aspecto negativo quando testando System-on-chip (SOC) ICs. O fluxo corrente de desenvolvimento de um IC insere scan chains e gera automaticamente padrões de teste de scan para alcançar uma alta cobertura para o teste de manufatura. Técnicas de compressão de dados provaram ser muito úteis para reduzir o custo de teste enquanto reduzem o volume de dados e o tempo de aplicação dos testes. Esse trabalho propõe o reuso de padrões de teste comprimidos usados durante o teste de manufatura para implementar um LBIST com objetivo de testar o circuito quando ele já está em campo. O mecanismo LBIST proposto objetiva descobrir defeitos que podem ocorrer devido ao desgasto do circuito. Uma arquitetura e um fluxo de desenvolvimento semi-automático do mecanísmo LBIST baseado em padrões de teste de scan são propostos e validados usando um SoC real como caso de teste

Yes

L'activité de test est une partie de plus en plus importante dans les développements logiciels. Cette activité de test est souvent longue et répétitive, les travaux entrepris dans cette thèse ont pour objectif de décharger l'ingénieur de test des tâches les plus répétitives de la synthèse de tests. Notre approche, dans le cadre du test de conformité, se base sur le fait qu'il existe différents niveaux d'abstraction pour définir des tests les tests exécutables pour une cible technologique, les tests abstraits qui sont indépendants de la technologie et les objectifs de test qui ne représentent que partiellement le chemin d'un test dans la spécification. Nos travaux portent sur deux points. le premier point vise à réduire l'effort alloué à la conception des tests. Pour cela nous définissons un nouveau niveau d'abstraction : les schémas de test qui offrent une abstraction supplémentaire sur les instances et valeurs manipulées. L'outil TObiAs a été développé au cours de la thèse pour aider à la conception des schémas de test, les déplier en objectifs de test ou en cas de test, puis concrétiser ces cas de test. le deuxième point étudie la portée d'un schéma de test en mesurant sa couverture de la spécification, au niveau d'abstraction du schém de test. Pour ce faire nous étudions les relations entre les niveaux d'abstraction de test et la spécification. Nous présentons l'intérêt de proposer une notion de couverture au niveau des schémas de test en construisant une abstraction de la spécification ainsi que l'outil CoPAS que nous avons créé pour calculer la couverture a priori.