This thesis work presents a simple and practical technique for seamlessly texturing quadrilateral meshes. Using this technique, an isotropic homogeneous texture can be mapped to any quadrilateral mesh without any discontinuity or singularity in the resultant texturing. The method involves organizing a set of square texture tiles that satisfy specific boundary conditions into one texture image file which is called a tiled texture. Based on the tiled textures, we have developed an extremely simple texture mapping algorithm that randomly assigns one tile to every patch in any given quadrilateral mesh. The mapping technique developed yields singularity free textures, regardless of the singularities existing in the quadrilateral mesh, gives seamless and continuous boundaries across textures and provides an aperiodic and interesting look to the entire textured surface.

Two primary types of multiplayer gaming have emerged over the years. The first type involves co-located players on a shared display, and typically caps at four players. The second type of gaming provides a single display for each player. This type scales well beyond four players, but places no requirement on co-location. This paper will attempt to combine the best of both worlds via high-resolution, highly-multiplayer gaming. Over the past few years, there has been a rise in the number of extremely high-resolution, tiled displays. These displays provide an enormous amount of screen space to work with. This space was used to allow twelve co-located players to play a game together. This study accomplishes three things: we designed and built PyBomber, a high-resolution and highly multiplayer game for up to twelve players; secondly, user trials were conducted to see whether this type of gaming is enjoyable as well as to learn what sorts of social interactions take place amongst so many players; lastly, the lessons learned were generalized into design criteria for future high-resolution games. Results show that with more people, much more of the time during a game was filled with vocal interactions between players. There were also more physical movements in the larger games. Over the course of this study, we learned that good high-resolution games will: decide between a singular gameplay area and split views, use the physical space in front of the display, provide feedback that is localized to each player, and utilize input devices appropriately. / Master of Science

The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures. This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply. It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control. / Report code: LiU-TEK-LIC-2006:36.

Numeric hydrologic models can aid in water resource management by providing predictive simulations of water behavior. As computers become more advanced, the models developed also become more complex using more data to represent larger areas for forecasting hydrologic behavior. Unfortunately, as the simulations use more data, the output often becomes difficult to manage and share without investing time and effort into setting up server environments or decreasing the quality of the output to compensate for an efficient and effective user experience. A proposed solution to facilitate the accessibility of massive hydrologic model output is through the web-based visualization tool developed at Carnegie Mellon University called Time Machine. For a more efficient and automated workflow, a Python tool named TMAPS was developed from this research for rendering hydrologic model results, geoprocessing the rendered output, and generating Time Machines seamlessly. The tool can be installed from the CI-WATER GitHub repository and allows the user to 1) select the output parameters and visualization settings desired to be rendered, 2) run the code on a local or HPC setup, and 3) use a web browser interface to view the tiled transient results seamlessly while maintaining high quality. Currently, the only hydrologic model supported is ADHydro - a large-scale high-resolution multi-physics watershed simulation. In an effort to facilitate organizing the library of Time Machine products, an app was created through Tethys - a server-based Django application designed to aid in the development and sharing of water resource engineering apps.

<p>The ever shrinking size of the MOS transistors brings the promise of scalable Network-on-Chip (NoC) architectures containing hundreds of processing elements with on-chip communication, all integrated into a single die. Such a computational fabric will provide high levels of performance in an energy efficient manner. To mitigate emerging wire-delay problem and to address the need for substantial interconnect bandwidth, packet switched routers are fast replacing shared buses and dedicated wires as the interconnect fabric of choice. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as 3D graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. Therefore, this work focuses on two key building blocks critical to the success of NoC design: high performance, area and energy efficient router and floating-point processor architectures.</p><p>This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power, with no performance penalty over a published design. In a 150nm six-metal CMOS process, the 12.2mm2 router contains 1.9 million transistors and operates at 1GHz at 1.2V. We next present a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulate loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. Combined algorithmic, logic and circuit techniques enable multiply-accumulates at speeds exceeding 3GHz, with single-cycle throughput. Unlike existing FPMAC architectures, the design eliminates scheduling restrictions between consecutive FPMAC instructions. The optimizations allow removal of the costly normalization step from the critical accumulate loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In addition, an improved leading zero anticipator (LZA) and overflow detection logic applicable to carry-save format is presented. In a 90nm seven-metal dual-VT CMOS process, the 2mm2 custom design contains 230K transistors. The fully functional first silicon achieves 6.2 GFLOPS of performance while dissipating 1.2W at 3.1GHz, 1.3V supply.</p><p>It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results from key building blocks demonstrate the feasibility of pushing the performance limits of compute cores and communication routers, while keeping active and leakage power, and area under control.</p> / Report code: LiU-TEK-LIC-2006:36.

This research presents the initial studies and results on shield design for Shape-Shifting Surfaces (SSSs) seeking maximum compression and maximum expansion of a unit-cell. Shape-Shifting Surfaces (SSSs) are multilayered surfaces that are able to change shape while maintaining their integrity as physical barriers. SSSs are composed of polygonal unit-cells, which can change side lengths and corner angles. These changes are made possible by each side and corner consisting of at least two different shields, or layers of material. As the layers undergo relative motion, the unit-cell changes shape. In order for the SSS to retain its effectiveness as a barrier, no gaps can open between different layers. Also, the layers cannot protrude past the boundaries of the unit-cell. Based on these requirements, using equilateral triangle unit-cells and triangular shields, a design space exploration was performed to determine the maximum deformation range of a unit-cell. It was found that the triangular shield that offered maximum expansion and compression ratio is a right triangle with one angle of 37.5 degrees and its adjacent side equal to 61% of the side of the unit-cell. The key contribution of this paper is a first algorithm for systematic SSS shield design. Possible applications for SSSs include protection, by creating body-armor systems; reconfigurable antennas able to broadcast through different frequencies; recreational uses, and biomedical applications.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.56-59).

Video streaming is used daily by people around the world, plays a big role in many Internet users daily lives, and are today responsible for the majority of the Internet traffic. As 360 video streaming services become increasingly popular and each such user session requires much higher bandwidths than traditional video streaming, optimized solutions for this type of video is becoming increasingly important. One method that has been proposed to reduce the bandwidth usage is the usage of proxy servers. In this thesis, we evaluate custom-adapted prefetching policies that tries to improve the users Quality of Experience (QoE). Defining a prefetching policy for something adaptive as 360 video brings challenges that need to be simulated before release in the real world. Without proper testing the prefetch policy can do more harm than good by flooding the network with unnecessary amount of transmissions. Prior research has shown that the QoE of HTTP-based adaptive streaming (HAS) clients can be improved with content-aware prefetching (e.g., Krishnamoothi et al. 2013). However, there have been limited prior work adapting and evaluating such policies in the context of 360 streaming. This thesis presents a simulation-based evaluation of proxy-assisted 360solutions that includes custom designed prefetching polices. The main contributions of the thesis are as follows:First, we implement four types of proxy-assisted prefetching policies and simulate these under two scenarios with different networks conditions. One scenario simulate a network environment with a bottleneck located between the client and proxy while the other scenario simulates a network environment with the bottleneck located between the proxy and server. The cooperation between the client and proxy is evaluated for each scenario and prefetching policy. Second, we evaluate the proxy-assisted prefetching policies in comparison with baselines and each other, in regards of their ability to improve the viewers QoE. Our results show that the bottleneck location has major impact on proxy-performance and that simple prefetching policies can enable clients to download bigger loads of data, which have a significant effect on viewers QoE. Considering that 360 videos require much higher bandwidth then traditional video streaming, service providers may consider integrating prefetching policies for 360 video streaming.

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The decreasing price of displays has enabled exploration of ever-larger high-resolution displays. Previous research has shown that as the display grows larger, users prefer to physically navigate, which has proven benefits. However, increasing the display size so radically creates a new difficulty in interaction. The paradigm has changed from sitting at a desktop computer to taking users' physical navigation into account and designing more mobile interactions. Currently, when users move, they change the scale at which they are viewing information without changing the interaction scale. This is a problem because tasks change at different levels of visual scale. Mulitscale interaction aims to exploit users’ movement by linking it to interaction, changing the interaction scale depending on users’ distance from the display. This work accomplishes three things: first, we define the design space of multiscale interaction; secondly, through a case study, we explore the design issues for a specific area of the design space; lastly, we evaluate one application through a user study that compares it to two other interaction types. We wanted to know, do users in fact benefit from the linkage of physical navigation with interaction? Results show a trend of a natural link between user distance and interaction scale, even with the other techniques that did not enforce this link. In addition, multiscale interaction benefits from the link by having more consistent performance. They also show that while participants using multiscale interaction tend to move more, they benefit from this additional movement, unlike with the other interaction types. / Master of Science