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Graduation date: 2006 / Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion.

Digital silicon photomultipliers (dSiPMs) and single-photon avalanche diode (SPAD) imagers are optical sensing systems formed from the integration of time-to-digital converters (TDCs) with arrays of highly sensitive photodetectors known as SPADs. TDCs are high-performance mixed-signal circuits capable of timestamping events with picosecond level resolution. The digital operation mechanisms of SPADs allow for their outputs to be sent to TDCs, where the timestamps of individual photon detections are recorded. In recent years, time-resolved SPAD-based sensors have been a heavily studied topic due to their exceptional performance potential in biomedical imaging applications, including time-of-flight (ToF) positron emission tomography (PET), fluorescence lifetime imaging microscopy (FLIM), and diffuse optical tomography (DOT). This work targets the optimization of these sensors in low-cost standard complementary metal-oxide-semiconductor (CMOS) processes. Firstly, this thesis provides a detailed review of the work accomplished in CMOS TDCs and their integration in SPAD-based sensors. Next, a feedback time amplification TDC was designed and tested in the TSMC 65 nm process that can achieve < 5 ps timing resolution in a very compact area of 0.016 mm2. The design is then described for a multi-time-gated array of p+/n-well SPADs that aims to mitigate SPAD dark noise while providing high-speed imaging by applying shifted gate windows simultaneously to an array of SPADs. The p+/n-well SPAD is first characterized in a passive quench configuration where it demonstrated a maximum dark count rate of 44.9 kHz, 18.1% peak PDP at 420 nm, and 0.82 ns timing jitter at a 0.7 V excess bias. While the current multi-time-gated prototype is not fully functional, the measurement results for individual pixels of the multi-time-gated array showed a 3.25 ns median gate window with a 2.2x 10-4 dark count probability for a 0.7 V excess bias, with 440 ps timing resolution and ~1 LSBrms timing jitter. Based on the results, limitations of the current design and sources for future improvement are then discussed in detail. / Thesis / Master of Applied Science (MASc) / Medical imaging plays a key role in the diagnosis of diseases like cancer, and as such, the optimized performance of medical imaging systems is a large area of research. Recently, highly sensitive photodetectors known as single-photon avalanche diodes (SPADs) were integrated with high-performance timing circuits known as time-to-digital converters (TDCs) to form digital silicon photomultipliers (dSiPMs) and SPAD imagers. DSiPMs and SPAD imagers are capable of timestamping the detection of individual photons with a very high level of accuracy in order to generate biomedical images. This thesis focuses on the design and measurement of these sensors using standard fabrication processes with the aim of working towards high-performance medical imaging sensors at a low cost. Firstly, we review the results achieved in TDCs and SPAD-based sensors within the recent literature. Following that, we present the design and performance results of a custom-designed TDC that aims to achieve state-of-the-art performance within a small area in order to maintain low-cost and optimal integration with SPADs. Next, the design is described for an array of custom time-gated SPADs with integrated TDCs. Finally, the SPAD is characterized in two different configurations to identify sources of improvement for future design iterations.

Fluorescence lifetime imaging (FLIM) has the potential to provide rapid screening and detection of diseases. However, time-resolved fluorescence measurements require high-performance detectors with single-photon sensitivity and sub-nanosecond time resolution. These systems should also be compact, reliable, inexpensive, and easily deployable for laboratory and clinical applications. It is with these applications in mind that the development of single photon avalanche diodes (SPAD) and time-to-digital converter (TDC) prototype integrated circuits (IC) in standard digital CMOS have been pursued in this thesis. SPAD and TDC ICs were designed and fabricated in 130 nm IBM CMOS technology and then intensively studied. Several different SPAD pixels were modeled and designed, and the electro-optical performance was characterized and comparatively studied. By repurposing existing design layers of a standard CMOS process, the fabricated SPAD pixel test structures achieved up to 20× improvement of dark count rate (DCR) compared to previous designs. Optical measurements also showed up to 10× improvement in the detection limits for low-level light. Detailed dark noise characterization was performed at various temperatures using free-running and time-gated modes of operation. Optimal operating conditions were found for minimal afterpulsing effects. The SPAD’s capability to accurately measure fast fluorescence decays was also demonstrated in a practical setting with the lifetime measurements of two fluorophores, Rhodamine 6G and Ruby crystal, which have fluorescence lifetimes of approximately 4 ns and 3 ms, respectively. A fast and accurate TDC prototype circuit for time-correlated single-photon counting (TCSPC) applications was designed, fabricated and characterized. With a coarse-fine delay line architecture, the TDC size was reduced without compromising its linearity and jitter performance. Extensive characterization of the fabricated SPAD and TDC ICs shows that the measured performance met the stated design goals. / Thesis / Doctor of Philosophy (PhD)

This bachelor thesis has been performed at Saab Dynamics AB in Karlskoga, with the purpose to design simulation models and analyze the technology study for distance measurement based on Time Of Flight (TOF) -principle. The distance measurement is implemented by short laser pulses and Time-to-Digital Converter (TDC). This method uses the time difference between when the laser pulse is transmitted to the time when its reflection from an object returns to the detector. With this technology as a starting point for this thesis, an analysis has been made by looking at the subsystems when it gets affected by different parameters. The simulation will give an expected result which has been compared with the measurement results. On this basis a ranking of the parameters according by the influence of the functionality has been delivered. / Det här examensarbetet har utförts vid Saab Dynamics AB i Karlskoga med syftet att modellera och analysera en teknikstudie för avståndsmätning baserad på Time-Of-Flight-principen (TOF-principen). Avståndsmätningen genomförs med korta laserpulser och Time-to-Digital Converter (TDC). Det är en metod för avståndsmätning som baseras på tidsskillnaden från den tidpunkt då laserpulsen skickas från laserdioden till den tidpunkt då fotodioden har detekterat den reflekterade laserpulsen. Med den nya teknikstudien som utgångspunkt för arbetet har en analys på hur avståndsmätarens delsystem påverkats av olika parametrar genomförts där förväntat resultat har jämförts med mätresultat. Med detta som grund har en rangordning av parametrarna efter hur stor inverkan de har på funktionaliteten levererats.

With the rapid advances in process technologies, the performance of state-of-the-art integrated circuits is improving steadily. The drive for higher performance is accompanied with increased emphasis on meeting timing constraints not only at the design phase but during device operation as well. Fortunately, technology advancements allow for even more precise control of the timing of digital signals, an advantage which can be used to provide solutions that can address some of the emerging timing issues. In this thesis, circuit and architectural techniques for the precise timing of digital signals are explored. These techniques are demonstrated in applications addressing timing issues in modern digital systems. A methodology for slow-speed timing characterization of high-speed pipelined datapaths is proposed. The technique uses a clock-timing circuit to create shifted versions of a slow-speed clock. These clocks control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit itself. In order to achieve higher resolutions than that of an inverter/buffer stage, a differential (vernier) delay line is commonly used. To allow for the design of differential delay lines with programmable delays, a digitally-controlled delay-element is proposed. The delay element is monotonic and achieves a high degree of transfer characteristics' (digital code vs. delay) linearity. Using the proposed delay element, a sub-1ps resolution is demonstrated experimentally in 0.18μm CMOS. The proposed delay element with a fixed delay step of 2ps is used to design a high-precision all-digital phase aligner. High-precision phase alignment has many applications in modern digital systems such as high-speed memory controllers, clock-deskew buffers, and delay and phase-locked loops. The design is based on a differential delay line and a variation tolerant phase detector using redundancy. Experimental results show that the phase aligner's range is from -264ps to +247ps which corresponds to an average delay step of approximately 2.43ps. For various input phase difference values, test results show that the difference is reduced to less than 2ps at the output of the phase aligner. On-chip time measurement is another application that requires precise timing. It has applications in modern automatic test equipment and on-chip characterization of jitter and skew. In order to achieve small conversion time, a flash time-to-digital converter is proposed. Mismatch between the various delay comparators limits the time measurement precision. This is demonstrated through an experiment in which a 6-bit, 2.5ps resolution flash time-to-digital converter provides an effective resolution of only 4-bits. The converter achieves a maximum conversion rate of 1.25GSa/s.

With the rapid advances in process technologies, the performance of state-of-the-art integrated circuits is improving steadily. The drive for higher performance is accompanied with increased emphasis on meeting timing constraints not only at the design phase but during device operation as well. Fortunately, technology advancements allow for even more precise control of the timing of digital signals, an advantage which can be used to provide solutions that can address some of the emerging timing issues. In this thesis, circuit and architectural techniques for the precise timing of digital signals are explored. These techniques are demonstrated in applications addressing timing issues in modern digital systems. A methodology for slow-speed timing characterization of high-speed pipelined datapaths is proposed. The technique uses a clock-timing circuit to create shifted versions of a slow-speed clock. These clocks control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9ps in 0.18μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit itself. In order to achieve higher resolutions than that of an inverter/buffer stage, a differential (vernier) delay line is commonly used. To allow for the design of differential delay lines with programmable delays, a digitally-controlled delay-element is proposed. The delay element is monotonic and achieves a high degree of transfer characteristics' (digital code vs. delay) linearity. Using the proposed delay element, a sub-1ps resolution is demonstrated experimentally in 0.18μm CMOS. The proposed delay element with a fixed delay step of 2ps is used to design a high-precision all-digital phase aligner. High-precision phase alignment has many applications in modern digital systems such as high-speed memory controllers, clock-deskew buffers, and delay and phase-locked loops. The design is based on a differential delay line and a variation tolerant phase detector using redundancy. Experimental results show that the phase aligner's range is from -264ps to +247ps which corresponds to an average delay step of approximately 2.43ps. For various input phase difference values, test results show that the difference is reduced to less than 2ps at the output of the phase aligner. On-chip time measurement is another application that requires precise timing. It has applications in modern automatic test equipment and on-chip characterization of jitter and skew. In order to achieve small conversion time, a flash time-to-digital converter is proposed. Mismatch between the various delay comparators limits the time measurement precision. This is demonstrated through an experiment in which a 6-bit, 2.5ps resolution flash time-to-digital converter provides an effective resolution of only 4-bits. The converter achieves a maximum conversion rate of 1.25GSa/s.

Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.

Single-photon avalanche diodes’ (SPADs) capabilities of detecting even a single photon with excellent timing resolution and compatibility with strong magnetic fields make them the most promising sensor for positron emission tomography imaging systems. With the advancements of silicon fabrication techniques, SPADs designed in standard planar complementary metal-oxide-semiconductor (CMOS) processes show competitive performance and a lower manufacturing cost. Additionally, CMOS SPADs have the potential for monolithic integration with other CMOS signal conditioning and processing circuits to achieve simple, low-cost, and high-performance imaging solutions. This work targets the design and optimization of SPAD sensors to improve their performance using low-cost standard CMOS technologies. Firstly, a detailed review on the SPADs in recent literature is presented. Then, the random telegraph signal (RTS) noise is investigated based on n+/p-well SPADs fabricated in a standard 130 nm CMOS process. Through the measurements and analysis, the RTS noise of a SPAD is found to correlate with its dark count rate and afterpulsing. Next, we design n+/p-well SPADs with field poly gates to improve the noise performance. Furthermore, a SPAD pixel, consisting of a p+/n-well SPAD and a compact and high-speed active quench and reset circuit is designed and fabricated in a standard TSMC 65 nm CMOS process. The post-layout simulations show that this pixel achieves a short 0.1 ns quenching time and a 3.35 ns minimum dead time. The measurement results show that the SPAD pixel has a dark count rate of 21 kHz, a peak photon detection probability of 23.8% at a 420 nm wavelength and a timing jitter of 139 ps using a 405 nm pulsed laser when the excess voltage is set to 0.5 V. Due to the short quenching time, almost no afterpulsing is observed even at a low operating temperature of -35 °C. Finally, a new differential quench and reset (QR) circuit consisting of two QR circuits on both the cathode and anode to quench and reset the SPAD through both terminals is proposed to reduce the reset time, to increase the count rate, to reduce the afterpulsing and to reject the common-mode noise. / Thesis / Doctor of Philosophy (PhD) / Positron emission tomography (PET) imaging is a powerful tool for diagnosis and assessment of cancers and tumors in the clinical field. Due to their capabilities of detecting even a single photon, excellent timing resolution, and their compatibility with magnetic fields to build PET/MRI (magnetic resonance imaging) multimodal imaging systems; single-photon avalanche diodes (SPADs) become the most promising sensor technology for PET imaging applications. SPADs fabricated in standard complementary metal-oxide-semiconductor (CMOS) technologies allow for a lower manufacturing cost and present the potential to integrate with other CMOS circuits to form a complete imaging system. In this thesis, random telegraph signal noise in SPADs is investigated first. Then, the poly gate is used in the design of an n+/p-well SPAD to improve the noise performance. In addition, a compact and high-speed SPAD pixel is designed and fabricated using an advanced standard CMOS process. Thanks to the fast quench and reset circuit, the SPAD pixel achieves a very short quenching time and a high-count rate. Finally, a differential quench and reset (QR) circuit consisting of two QR circuits on both the cathode and anode to quench and reset the SPAD through both terminals is proposed and studied.

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