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The study designs and constructs a three-phase to three-phase direct AC&ndash / AC matrix converter based surface mounted permanent magnet synchronous motor (PMSM) drive system. First, the matrix converter topologies are analyzed and the state-space equations describing the system have been derived in terms of the input and output variables. After that, matrix converter commutation and modulation methods are investigated. A four-step commutation technique based on output current direction provides safe commutation between the matrix converter switches. Then, the matrix converter is simulated for both the open-loop and the closed-loop control. For the closed-loop control, a current regulator (PI controller) controls the output currents and their phase angles. Advanced pulse width modulation and control techniques, such as space vector pulse width modulation and field oriented control, have been used for the closed-loop control of the system. Next, a model of diode-rectified two-level voltage source inverter is developed for simulations. A comparative study of indirect space vector modulated direct matrix converter and space vector modulated diode-rectified two-level voltage source inverter is given in terms of input/output waveforms to verify that the matrix converter fulfills the two-level voltage source inverter operation. Following the verification of matrix converter operation comparing with the diode-rectified two-level voltage source inverter, the simulation model of permanent magnet motor drive system is implemented. Also, a direct matrix converter prototype is constructed for experimental verifications of the results. As a first step in experimental works, filter types are investigated and a three-phase input filter is constructed to reduce the harmonic pollution. Then, direct matrix converter power circuitry and gate-driver circuitry are designed and constructed. To control the matrix switches, the control algorithm is implemented using a DSP and a FPGA. This digital control system measures the output currents and the input voltages with the aid of sensors and controls the matrix converter switches to produce the required PWM pattern to synthesize the reference input current and output voltage vectors, as well. Finally, the simulation results are tested and supported by laboratory experiments involving both an R-L load and a permanent magnet synchronous motor load. During the tests, the line-to-line supply voltage is set to 26 V peak value and a 400 V/3.5 kW surface mounted permanent magnet motor is used.

Conventional 2-level inverters have been quite popular in industry for drives applications. It used pulse width modulation techniques to generate a voltage waveform with high quality. For achieving this, it had to switch at high frequencies and also the switching is between 0 and Vdc. Also additional LC filters are required before feeding to a motor. 3-phase IM is the work horse of the industry. Several speed control techniques have been established namely the V/f control technique and for high performance, vector control is adopted. An electric drive system comprises of a rectifier, inverter, a motor and a load. each module is a topic by itself. This thesis work discusses the novel inverter topologies to overcome the demerits of a conventional 2-level inverter or even the basic multilevel topologies, for an electric drive. The word ‘multilevel’ itself signifies that inverter can generate more than two levels. The idea was first originated by Nabae, Takahashi and Akagi to bring an additional voltage level so that the waveform becomes a quasi square wave. This additional voltage level brought additional benefits in terms of reduced dv/dt and requirement of low switching frequency. But this was not without any cost. The inverter structure is slightly more complicated than a 2-level and also required more devices. But the advantage it gave was superior enough to such an extent that the above topology (popularly known as NPC) has become quite popular in industry. This topology was later modified to equalize the semiconductor losses among switches by replacing the clamping diodes with controllable switches and such topologies are popularly known as Active NPCs (ANPCs) because of the replacement of diodes with active switches. 3-level flying capacitors were then introduced where the additional voltage level is provided using charged capacitors. But this capacitor voltage has to be maintained at its nominal value during the inverter operation. An additional floating capacitor, which is an electrolytic capacitor is needed for this. Increasing the number of electrolytic capacitors reduces the reliability of the inverter drive since they are the weakest link in any inverters and its count has to be kept to the minimum. By using a H-bridge cell in each of the three phases, three voltage levels can be easily obtained.This is commonly known as Cascaded H-bridge (CHB) multilevel inverter. The above three topologies have been discussed with respect to generation of three pole voltage levels and these topologies are quite suited also. A higher number of voltage levels will reduce the switching frequency even lesser and also the dv/dt. On increasing the number of levels further and further, finally the inverter need not do any PWM switching and just generating the levels is sufficient enough for a good quality waveform and also low dv/dt. But when the above topologies are scaled for more than three voltage levels, all of them suffer serious drawbacks which is briefly discussed below. The diode clamped inverter (known as NPC if it is 3-level), when extended to more than three levels suffers from the neutral point balancing issue and also the count of clamping diodes increase drastically. FC inverters, when extended beyond 3-level, the number of electrolytic capacitors increases and also balancing of these capacitors to their nominal voltages becomes complicated. In the case of multilevel CHB, when extended beyond 3-level, the requirement of isolated DC sources also increases. To generate isolated supplies, phase shifting transformer and 8, 12 or 24 pulse diode rectifier is needed which increases the weight , size and cost of the drive. Therefore its application is limited. In this thesis, the aim is to develop a novel method to develop a multilevel inverter without the drawbacks faced by the basic multilevel topologies when scaled for higher number of voltage levels. This is done through stacking the basic or hybrid combination of these basic multilevel topologies through selector switches. This method is experimentally verified by stacking two 5-level inverters through a 2-level selector switch (whose switching losses can be minimized through soft cycle commutation). This will generate nine levels.Generating 9-levels through scaling the basic topologies is disadvantageous, the comparison table is provided in the thesis. This is true for any higher voltage level generation. Each of the above 5-level inverter is developed through cascading an FC with a capacitor fed H-bridge. The device count can be reduced by making the FC-CHB module common to the selector switches by shifting the selector switches between the DC link and the common FC-CHB module. Doing so, reduces the modular feature of the drive but the device count can be reduced. The FFT plot at different frequencies of operation and the switching losses of the different modules-FC, CHB and the selector switches are also plotted for different frequencies of operation. The next step is to check whether this method can be extended to any number of stackings for generation of more voltage levels. For this, a 49-level inverter is developed in laboratory by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading an FC with three CHBs. When there are 49 levels in the pole voltage waveform, there is no need to do any regular PWM since the output waveform will be very close to a sine wave even without any PWM switching. The technique used is commonly known in literature as Nearest Level Control (NLC). This method of stacking and cascading has the advantage that the FC and the CHB modules now are of very low voltages and the switching losses can be reduced. The switching losses of the different modules are calculated and plotted for different operating frequencies in the thesis. To reduce the voltages of the modules further, a 6-phase machine has been reconfigured as a 3-phase machine, the advantage being that now the DC link voltage requirement is half of that needed earlier for the same power. This further reduces voltages of the modules by half and this allows the switches to be replaced with MOSFETs, improving the efficiency of the drive. This topology is also experimentally verified for both steady state and transient conditions. So far the research focussed on a 3-phase IM fed through a stacked MLI. It can be observed that a stacked MLI needs as many DC sources as the number of stackings. A 6-phase machine apart from reduced DC link voltage requirement, has other advantages of better fault tolerant capability and better space harmonics. They are serious contenders for applications like ship propulsion, locomotive traction, electric vehicles, more electric aircraft and other high power industrial applications. Using the unique property of a 6-phase machine that its opposite windings always draw equal and opposite current, the neutral point (NP) (formed as a result of stacking two MLIs) voltage can be balanced. It was observed that the net mid point current drawn from the mid point can be made zero in a switching interval. It was later observed that with minimal changes, the mid point current drawn from the NP can be made instantaneously zero and the NP voltage deviation is completely arrested and the topology needs only very low capacity series connected capacitors energized from a single DC link. This topology is also experimentally verified using the stacked 9-level inverter topology discussed above but now for 6-phase application and experimental results are provided in the thesis. Single DC link enables direct back to back conversion and power can be fed back to the mains at any desired power factor. All the experimental verification is done on a DSP (TMS320F28335) and FPGA (Spartan 3 XCS3200) platform. An IM is run using V/f control scheme and the above inverter topologies are used to drive the motor. The IGBTs used are SKM75GB123D for the stacked 9-level inverter in the 3-phase and 6-phase experiments. For the 49-level inverter experiment, MOSFETs-IRF260N were used. Both steady state and transient results ensure that the proposed inverter topologies are suitable for high power applications.

The falling cost of batteries, along with an increasing need to cut emissions, has spurred significant interest in the electrification of vehicles. In addition, as semiconductor devices have evolved, the research for electric vehicles with higher battery voltage has increased. The traction inverter is an important part of the electric power train and can account for a substantial portion of the drive train’s losses. This thesis therefore models, simulates, and studies the losses for a convectional Two-Level (2L) inverter and a Three-Level T-Type (3LT) inverter utilizing Silicon Carbide (SiC) MOSFETs and compares the two inverter topologies in terms of efficiency. The rated power of the inverters is 120 kW at a DC voltage of 800 V. The theoretical basis of SiC MOSFET and its reverse conduction, operation of 2L and 3LT inverter topologies, and Space Vector Pulse Width Modulation (SVPWM) technique are introduced in the initial part of the thesis. To estimate switching and conduction losses, Simulink is used to model and simulate an electric drive system. These estimated losses are then utilized to develop efficiency maps for both topologies over the complete speed-torque range. Based on the efficiency comparison, the 3LT topology outperforms the 2L topology for any requested torque in the medium to the high-speed range, which is typical of highway driving. In the low-speed, high-torque region, which is typical of city driving, the 2L topology is superior. The efficiency of each topology is affected by switching frequency, device junction temperature, and DC-link voltage. However, the comparison reveals that the maximum average difference in efficiency is 0.35%, with the 3LT topology being superior. Finally, the efficiency differences between the two inverter topologies are minimal. As a result, it may be concluded that the two topologies perform similarly. Thus, it can be inferred that comparing the efficiency of the two topologies should not be the sole criterion for selecting which topology should be used for the electric drive. / Den sjunkande kostnaden för batterier, tillsammans med ett ökande behov av att minska utsläppen, har lett till ett stort intresse för elektrifiering av fordon. Dessutom, har utvecklingen av halvledare lett till en ökning inom forskningen av elfordon med högre batterispänning. Traktionsomriktaren är en viktig del av den elektriska drivlinan och kan stå för en stor del av de totala förlusterna i drivlinan. I denna rapport modelleras, simuleras och studeras därför förlusterna i en konventionell omriktare med två nivåer (2L) och en T-typ omriktare med tre nivåer (3LT). Båda topologierna använder kiselkarbid (SiC) MOSFETs i jämförelsen av resultaten med avseende på verkningsgrad. Inverterarnas nominella effekt är 120 kW vid en likspänning på 800 V. Den teoretiska grunden för SiC MOSFET och hur de fungerar, hur 2L- och 3LT-inverterstopologierna fungerar samt tekniken för Space Vector Pulse Width Modulation (SVPWM) presenteras i rapporten. För att uppskatta switch- och ledningsförluster används Simulink för att modellera och simulera det elektriska drivsystemet. De uppskattade förlusterna används sedan för att utveckla verkningsgradskartor för de båda topologierna över hela det operativa området. Baserat på verkningsgradsjämförelsen mellan topologierna så presterar 3LT-topologin bättre än 2L-topologin i driftspunkter i medelhöga till höga hastigheter, vilket är typiskt för motorvägskörning. Vid låga hastigheter med högt vridmoment, vilket är typiskt för stadskörning, är 2L-topologin bättre. Verkningsgraden för de båda topologierna påverkas av switchfrekvensen, halvledarens temperatur samt DC-länkspänning. Jämförelsen visar dock att den största genomsnittliga skillnaden i verkningsgrad mellan de två topologierna är 0,35%, där 3LT-topologin är bättre. Sammanfattningsvis så är skillnaderna i verkningsgrad mellan de två topologierna minimala, vilket innebär att de båda topologierna har liknande prestanda med avseende på verkningsgrad. Man bör därför inte bara ha verkningsgrad som det enda kriteriet vid val av topologi för elektriska drivlinor.