This research is focused on identifying an appropriate design for a reconfigurable Body Area Network (BAN). In order to investigate the benefits and drawbacks of the proposed design, a BAN system prototype was built. This system consists of two distinct node types: a slave node and a master node. These nodes communicate using ZigBee radio transceivers. The microcontroller-based slave node acquires sensor data and transmits digitized samples to the master node. The master node is FPGA-based and runs uClinux on a soft-core microcontroller. The purpose of the master node is to receive, process and store digitized sensor data. In order to verify the operation of the BAN system prototype and demonstrate reconfigurability, a specific application was required. Pattern recognition in electrocardiogram (ECG) data was the application used in this work and the MIT-BIH Arrhythmia Database was used as the known data source for verification. A custom test platform was designed and built for the purpose of injecting data from the MIT-BIH Arrhythmia Database into the BAN system. The BAN system designed and built in this work demonstrates the ability to record raw ECG data, detect R-peaks, calculate and record R-R intervals, detect premature ventricular and atrial contractions. As this thesis will identify, many aspects of this BAN system were designed to be highly reconfigurable allowing it to be used for a wide range of BAN applications, in addition to pattern recognition of ECG data.

Chemnitz, Techn. Univ., Diplomarb., 2008.

<p>Voice over IP technology (VoIP) has recently gained popularity among consumers. Many popular VoIP services exist only as software for PCs. The need of taking such services out of the PC, into a stand-alone device has been discovered, and this thesis work deals with the development of such a device. The thesis work is done for Häger Scandinavia AB, a Swedish telephone manufacturer. This thesis work covers the design of a complete prototype of a table-top VoIP telephone running an embedded Linux Operating system. Design areas include product development, hardware design and software design.The result is a working prototype with hardware and corresponding Linux device drivers. The prototype can host a Linux application adapted to it. Conclusions are that the first hardware version has worked well and that using an open-source operating system is very useful. Further work consists of implementing a complete telephony software application in the system, evaluation of system requirements and adapting the prototype for a commercial design.</p>

As the technology of SOC has greatly improved and man want much more powerful mobile device, the invention of multi-task device for vehicle are predictable. This theme contains integration of GPS and GSM/GPRS, using a ARM7-core embedded platform functioning wireless communication and global positioning, and also taking advantage of the open-source uClinux to accomplish the multi-task monitoring & burglarproof system for vehicle. Moreover, we design a server end for multi-user to monitor and to remote control vehicles online. Combined with e-map system sold in the market, we can monitor all mobile devices any time, anywhere. We also implement this as a value added service for cellular phone to make it more than a communication or multimedia device. Due to the high cell phone possession rate in Taiwan, we can easily construct a system to monitor and to control our lovely car by cell phone, without extra effort and additional hardware.

Voice over IP technology (VoIP) has recently gained popularity among consumers. Many popular VoIP services exist only as software for PCs. The need of taking such services out of the PC, into a stand-alone device has been discovered, and this thesis work deals with the development of such a device. The thesis work is done for Häger Scandinavia AB, a Swedish telephone manufacturer. This thesis work covers the design of a complete prototype of a table-top VoIP telephone running an embedded Linux Operating system. Design areas include product development, hardware design and software design.The result is a working prototype with hardware and corresponding Linux device drivers. The prototype can host a Linux application adapted to it. Conclusions are that the first hardware version has worked well and that using an open-source operating system is very useful. Further work consists of implementing a complete telephony software application in the system, evaluation of system requirements and adapting the prototype for a commercial design.

This project investigates a self-reconfiguring rSoC (reconfigurable System on Chip) system which automatically and dynamically loads peripheral controllers, based on the peripherals connected to the system. The Xilinx Virtex-II FGPA, which supports dynamic partial reconfiguration, is used as the experimental target. To implement the system, three main areas are investigated: the peripheral auto detection, the dynamic partial reconfiguration mechanism on the FPGA, and the supporting software. The system core is designed as two defined areas on a single FPGA chip. A fixed area is used for the constant logic circuits (such as soft-core CPU) and partial reconfiguration (PR) slots are used for changeable peripheral controllers. The autoconfiguration process involves three different steps: peripheral auto detection, loading of a peripheral hardware interface configuration, and loading of a peripheral software driver. In our system, we successfully implement the mechanism of peripheral dynamic loading on the rSoC system. Four novel features are provided in the system: 1) Peripheral auto detection. Peripheral boards are automatically detected by the system when connected to the system. 2) Peripheral controller hardware bitstream and software driver dynamic loading. The required peripheral controller hardware bitstream for the connected peripheral board is automatically searched for and loaded by the operating system, as well as the required software driver. Manual operations on these processes are also supported. 3) Individual interface to external environment. Each PR slot provides individual interface to peripheral boards. It is configured by each peripheral controller for board-specific connection. 4) The existing system is extensible. The partial reconfiguration mechanism provided in this project supports at least two PR slots. On higher capacity FPGAs, the number of PR slots could be increased. In our existing system, the time used for the dynamic partial reconfiguration process, including the hardware bitstream loading and the software driver loading, is in the order of 10-20ms, which is an insignificant fraction of the Linux boot time.

El presente trabajo de memoria tuvo el objetivo de realizar el desarrollo de una interfaz capaz de realizar el control de un bus I2C mediante el acceso a este desde una red Ethernet. El estudio de las posibles soluciones se centró en los principales requerimientos del sistema, los cuales fueron, el costo de la solución y la escalabilidad de este sistema, siendo capaz de llegar con la misma arquitectura a una velocidad de enlace de 1Gbps. Dicho estudio se realizó para una empresa de radiodifusión llamada Continental Lensa, la cual busca desarrollar una plataforma de conexión que logre ser incluida en sus equipos de radiodifusión como producto de valor agregado, con la finalidad de que la empresa obtenga una plataforma estándar para realizar el manejo de equipos remotamente a través de esta interfaz. Para la realización de este desarrollo, se escogió entre toda una gama de soluciones posibles, el uso de dispositivos semiconductores FPGA, en los cuales es posible producir la escalabilidad necesaria ya que existen núcleos capaces de operar a 1Gbps. El resultado de tal estudio, demostró que la mejor solución es aquella que consta de la utilización de un procesador embebido implementado en la lógica del dispositivo FPGA, el cual no produce costos extras por cada dispositivo nuevo realizado. En este dispositivo, además se integró un sistema operativo Open Source basado en Linux llamado uClinux sobre el cual se realizará cada uno de los programas. El controlador del bus I2C necesario se realiza mediante un núcleo de libre distribución, obtenido desde Internet, el cual es controlado desde el sistema operativo, con lo cual se muestra que es posible añadir nuevos periféricos a este sistema sin aumentar los costos de la solución y además se logra el control deseado. En cuanto a la interfaz WEB, fué desarrollada mediante Applets, de modo de poder tener un elemento, el cual pueda ser configurado gráficamente en la empresa y que pueda ser visto desde cualquier computador, previa instalación de la maquina virtual de Java, en el PC que permita la visualización de la aplicación. Posteriormente se analizó las tasas de transferencias que se pueden alcanzar con el sistema implementado y además se presenta una explicación acerca de todas las herramientas necesarias para la realización de este sistema. Como conclusión del desarrollo realizado, se obtuvo un sistema, capaz de producir una reducción de costos, teniendo una gama de posibilidades para su extensión, modificando la lógica implementada de acuerdo a las necesidades y requerimientos de la empresa, en la cual se trabajó.

Made available in DSpace on 2014-06-12T16:00:24Z (GMT). No. of bitstreams: 2 arquivo6554_1.pdf: 3066452 bytes, checksum: 91820a83661287c92ba4438dd8c7a4d7 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2007 / Os dispositivos lógicos programáveis, FPGAs (Field Programmable Gate Arrays) há algum tempo têm sido uma tecnologia interessante para prototipação de circuitos digitais. Porém, esta realidade tem mudado à medida que a capacidade computacional destes dispositivos tem aumentado e o custo diminuído. Além disso, os FPGAs atuais podem utilizar menos energia que uma CPU convencional utilizaria para realizar a mesma computação. Outra característica, que traz grandes possibilidades, é a capacidade de reconfiguração em tempo de execução (reconfiguração dinâmica). Todos estes avanços permitiram a utilização dos FPGAs não só em aplicações típicas como sistemas embarcados mas também em sistemas de alto desempenho, que realizam processamento massivo de dados. Contudo, apesar das diversas vantagens apresentadas, esta tecnologia ainda não é largamente utilizada para realizar computação. Várias são as razões para isso, entre elas a exigência de um mínimo conhecimento em eletrônica digital para possibilitar o desenvolvimento dos IP-Cores; a complexidade do processo de desenvolvimento destes sistemas; os custos elevados com licenças das ferramentas e com as plataformas de desenvolvimento e a pouca portabilidade das aplicações desenvolvidas. O objetivo deste trabalho é prover uma plataforma reconfigurável que seja capaz, através de um sistema operacional e de maneira eficiente, gerenciar os recursos oferecidos pelos FPGAs. A plataforma proposta recebeu o nome de Aquarius II e foi baseada na plataforma Aquarius desenvolvida no CIn-UFPE. A arquitetura desta plataforma é híbrida e consiste de um FPGA Stratix-II da Altera responsável pelo controle da reconfiguração e tráfego dos dados e de um FPGA Virtex-II da Xilinx que é o elemento reconfigurável propriamente dito. Foram incorporados a esta plataforma um módulo de comunicação (IPCommCore) que é responsável pelo tráfego de dados do sistema operacional para a memória do dispositivo reconfigurável, um device driver para que o sistema operacional uCLinux possa controlar a comunicação através deste módulo e também foi definida uma interface de comunicação padrão para os cores reconfiguráveis que vierem a ser implementados. Para validar esta interface foi implementado e validado um core multiplicador para o Virtex-II utilizado como estudo de caso. Esta plataforma permitirá que sejam realizadas pesquisas em áreas que buscam se beneficiar desta tecnologia, como desenvolvimento de sistemas embarcados e sistemas de alta performance. O desenvolvimento de sistemas computacionais que utilizam hardware reconfigurável em sua arquitetura ainda é pouco comum e complexo. No entanto, propostas como a apresentada neste trabalho procuram solucionar ou atenuar os problemas citados e mudar sensivelmente esta realidade tornando viáveis e mais populares soluções que utilizam esta tecnologia

<p>På Ericsson AB i Katrineholm finns ett tekniklaboratorium (Techlab), där den senaste tekniken för GPRS-system finns samlad. Till Ericssons tekniklaboratorium skulle en demo-applikation konstrueras. Applikationen ska illustrera hur en mobiltelefon av typen Ericsson T68 kan skicka en bild via Bluetooth till en LAN nod (BlipC11). Den är kopplad till ett GPRS-nätverk och ska i sin tur skicka vidare bilden till en mottagare på andra sidan nätet. </p><p>Rapporten ger en teoretisk bakgrund om Bluetooth och GPRS. Vidare i rapporten presenteras lösningsförslag och resultatet av examensarbetet. </p><p>Projektet har varit problemfyllt. De resultat och slutsatser som erhållits är att utrustningen som varit tillgänglig inte klarar av att handskas med bildobjekt. Det betyder att kravspecifikationen ej kunde fullföljas. Alternativa användningsområden för noden har undersökts, som WAP- eller webserver. En webserver samt olika applikationsexempel till noden är resultatet av detta examensarbete.</p> / <p>At Ericsson AB in Katrineholm is a technical lab (Techlab) located, where the latest technique for GPRS-systems is gathered. A demo-application where supposed to be build for Techlab. The demo-application shall demonstrate the capabilities of Bluetooth and GPRS. An Ericsson T68 mobile will wirelessly send an image across a Bluetooth link to a LAN access point (BlipC11). The access point will then transport the image further on to the GPRS-net to a receiver, at the other end of the net. </p><p>The report gives a theoretical background about Bluetooth andGPRS. In the report, methods and results of the final year project are presented. </p><p>During the project a several problems occurred. The results and the conclusions show that an image can’t be sent with the equipment that was handed out. This means that the assignment specification could not be fulfilled. Other scenarios with the LAN access point have been investigated. It could be used as a WAP- or webserver for example. A webserver and some application examples for the access point, is the result of this project.</p>

At IAV GmbH, Chemnitz, an embedded platform for high-performance sensor data acquisition has been developed. Sensor data is gathered and preprocessed by two digital signal processors (DSP) which communicate bidirectionally via dual-ported memory with the central controlling instance, a Freescale MCF5484 microcontroller running uClinux. The goal of this thesis is to design, implement, analyze and optimize a real-time communication protocol between both DSPs and the microcontroller. The challenges of this thesis can be defined as follows: • A uClinux driver for the dual-ported RAM must be implemented. This driver has to employ the microcontroller’s internal DMA engine and should be integrated into the Linux kernel’s DMA framework. • The DMA engine must be thoroughly analyzed. Especially interesting is its behavior when concurrently performing data transfers. Potential influence factors onto data transfer performance and timing predictability should be experimentally identified and quantitatively characterized, if possible. • Sensor data from the DSPs to the microcontroller has to meet real-time demands and must be prioritized in some way over status and parameter data from and to the DSPs. • Correct and efficient synchronization is a must. If possible, different synchronization schemes should be compared to each other. • The achievable performance in terms of guaranteed and maximum data throughput between DSP and microcontroller as well as end-to-end bandwidth has to be estimated. • Apart from the DMA engine analysis, a general evaluation of potential and achieved performance, timing predictability and the remaining microcontroller’s processing capacity (if any) should be executed.