Development of software-intensive systems such as embedded systems for telecommunications, avionics and automotives occurs under severe quality, schedule and budget constraints. As the size and complexity of software-intensive systems increase dramatically, the problems originating from the design and specification of the system architecture becomes increasingly significant. Architecture-based development approaches promise to improve the efficiency of software-intensive system development processes by reducing costs and time, while increasing quality. This paradox is partially explained by the fact that the system architecture abstracts away unnecessary details, so that developers can concentrate both on the system as a whole, and on its individual pieces, whether it's the components, the components' interfaces, or connections among components. The use of architecture description languages (ADLs) provides an important basis for verification since it describes how the system should behave, in a high level view and in a form where automated tests can be generated. Analysis and testing based on architecture specifications allow detection of problems and faults early in the development process, even before the implementation phase, thereby reducing a significant amount of costs and time. Furthermore, tests derived from the architecture specification can later be applied to the implementation to see the conformance of the implementation with respect to the specification. This thesis extends the knowledge base in the area of architecture-based verification. In this thesis report, an airplane control system is specified using the Architecture Analysis and Description Language (AADL). This specification will serve as a starting point of a system development process where developed architecture-based verification algorithms are applied.

Software testing is an important process for ensuring the quality of the software. As the complexity of the software increases, traditional means of manual testing becomes increasingly more complex and time consuming. In most embedded systems, designing software with as few errors as possible is often critical. Resource usage is also of concern for proper behavior because of the very nature of embedded systems.  To design reliable and energy-efficient systems, methods are needed to detect hot points of consumption and correct them prior to deployment. To reduce testing effort, Model-based testing can be used which is one testing method that allows for automatic testing of model based systems. Model-based testing has not been investigated extensively for revealing resource usage anomalies in embedded systems. UPPAAL SMC is a statistical model checking tool which can be used to model the system’s resource usage. Currently UPPAAL SMC lacks the support for performing automatic test generation and test selection. In this thesis we provide this support with a framework for automatic test generation and test selection using mutation analysis, a method for minimizing the generated test suite while maximizing the fault coverage and a tool implementing the framework on top of the UPPAAL SMC tool. The thesis also evaluates the framework on a Brake by Wire industrial system. Our results show that we could for a Brake-by-wire system, simulated on a consumer processor with five mutants, in best case find a test case that achieved 100% mutation score within one minute and confidently identify at least one test case that achieved full mutation score within five minutes. The evaluation shows that this framework is applicable and relatively efficient on an industrial system for reducing continues resource usage target testing effort.

Model-based development is one of the most significant areas in recent research and development activities in the field of automotive industry. As the field of software engineering is evolving, model based development is gaining more and more importance in academia and industry. Therefore, it is desirable to have techniques that are able to identify anomalies in system models during the analysis and design phase instead of identifying them in development phase where it is difficult to detect them and a lot of time, effort and resources are required to fix them. Model checking is a formal verification technique that facilitates the identification of defects in system models during early stages of system development. There are a lot of tools in academia and industry that provide the automated support for model checking.  In this master thesis a vehicle control system of Scania the Fuel Level Display System is modeled in two different model checking tools; Simulink Design Verifier and UPPAAL. The requirements that are to be satisfied by the system model are verified by both tools. After verifying the requirements against the system model and checking the model against general design errors, it is established that the model checking can be effectively used for detecting the design errors in early development phases and can help developing better systems. Both the tools are analyzed depending upon the features supported. Moreover, relevance of model checking is studied with respect to ISO 26262 standard.

Quality assurance of dependable embedded systems is becoming increasingly difficult, as developers are required to build more complex systems on tighter budgets. As systems become more complex, system architects must make increasingly complex architecture design decisions. The process of making the architecture design decisions of an intended system is the very first, and the most significant, step of ensuring that the developed system will meet its requirements, including requirements on its ability to tolerate faults. Since the decisions play a key role in the design of a dependable embedded system, they have a comprehensive effect on the development process and the largest impact on the developed system. Any faulty architecture design decision will, consequently, propagate throughout the development process, and is likely to lead to a system not meeting the requirements, an unacceptable level of dependability and costly corrections. Architecture design decisions are in turn critical with respect to quality and dependability of a system, and the cost of the development process. It is therefore crucial to prevent faulty architecture design decisions and, as early as practicable, detect and remove faulty decisions that have not successfully been prevented. The use of Architecture Description Languages (ADLs) helps developers to cope with the increasing complexity by formal and standardized means of communication and understanding. Furthermore, the availability of a formal description enables automated and formal analysis of the architecture design. The contribution of this licentiate thesis is an architecture quality assurance framework for safety-critical, performance-critical and mission-critical embedded systems specified by the Architecture Analysis and Design Language (AADL). The framework is developed through the adaption of formal methods, in particular traditional model checking and model-based testing techniques, to AADL, by defining formal verification criteria for AADL, and a formal AADL-semantics. Model checking of AADL models provides evidence of the completeness, consistency and correctness of the model, and allows for automated avoidance of faulty architecture design decisions, costly corrections and threats to quality and dependability. In addition, the framework can automatically generate test suites from AADL models to test a developed system with respect to the architecture design decisions. A successful test suite execution provides evidence that the architecture design has been implemented correctly. Methods for selective regression verification are included in the framework to cost-efficiently re-verify a modified architecture design, such as after a correction of a faulty design decision. / Kvalitetssäkring av tillförlitliga inbyggda system är en ständigt växande utmaning då utvecklare av sådana system är tvungna att bygga allt mer komplexa system inom allt mer begränsade budgetar. Då komplexiteten av systemen ökar måste systemarkitekter göra allt mera komplicerade beslut om systemens arkitekturdesign. Processen att besluta arkitekturdesignen av ett tilltänkt system är det allra första, och det mest signifikanta, steget att försäkra att det utvecklade systemet kommer uppnå dess krav, inklusive krav på dess möjlighet att tolerera defekter. Då dessa designbeslut dessutom har en nyckelroll i designen av ett tillförlitligt inbyggt system har de en omfattande effekt på utvecklingsprocessen samt den största påverkan på det utvecklade systemet. På grund av detta kommer ett felaktigt beslut om arkitekturdesignen propagera igenom hela utvecklingsprocessen och sannolikt resultera i ett system som inte uppnår kraven, får en oacceptabel tillförlitlighetsnivå, och kostsamma korrigeringar. De är därmed kritiska med hänsyn till kvaliteten och tillförlitligheten av ett inbyggt system, och kostnaden av utvecklingsprocessen. Således är det kritiskt att förhindra felaktiga beslut om arkitekturdesign och, så tidigt som möjligt, detektera och avlägsna felaktiga beslut som inte har lyckats att förhindras. Användningen av språk för arkitekturbeskrivning hjälper utvecklare att hantera den ökande komplexiteten genom standardiserade kommunikationsmedel och förståelsemedel. Dessutom möjliggör en formell beskrivning automatiserad och formell analys av arkitekturdesignen. Bidraget av denna licentiatavhandling är ett formellt kvalitetssäkringsramverk för säkerhetskritiska, prestandakritiska och uppdragskritiska inbyggda system specificerade i arkitekturbeskrivningsspråket ”Architecture Analysis and Design Language” (AADL). Ramverket är utvecklat genom adaptionen av formella metoder, i synnerhet traditionella modellkontrolltekniker och modellbaserad testningstekniker, till AADL, med hjälp av att definiera formella verifikationskriterier för AADL och en formell AADL-semantik. Modellkontroll av AADL-modeller analyserar modellens fullständighet, konsistens och korrekthet och möjliggör automatisk undvikande av felaktiga arkitekturdesignbeslut, kostsamma korrigeringar och hot mot kvalitet och tillförlitlighet. Därutöver kan ramverket automatiskt generera testsviter från AADL-modeller för att testa ett utvecklat system mot den bestämda arkitekturdesignen. En lyckad testsvitexekvering garanterar att arkitekturdesignen är korrekt implementerad. Metoder för selektiv regressionsverifiering är inkluderade i ramverket för att på ett kostnadseffektivt tillvägagångssätt verifiera en, tidigare verifierad, arkitekturdesign som har blivit modifierad, såsom efter en korrigering av ett felaktigt designbeslut.

This thesis discusses autonomous vehicles. At first it contains describing development of these type of vehicles, how they work and discuss their future development. Further it describe tools which can be used for create model of autonomous vehicle. The thesis includes design, description of the development and testing of the model in the UPPAAL Stratego verification environment. The resulting model is a system of intercommunicating timed automata. The analysis of the model properties is based on the method of statistical verification. The model allows us to investigate behavior of an autonomous vehicle in situations which correspond to regular traffic.

Tato práce analyzuje ochranu citlivých dat na mobilních zařízeních a představuje metodu pro ochranu těchto dat před možností úniku informaci ze zařízení. Ochrana se zaměřuje na využívání zařízení, jak pro osobní účely, tak i v pracovním prostředí. Koncept navrženého řešení je implementován ve formě prototypu. Model implementace je verifikován s modelem požadovaného chování. Součástí práce jsou experimenty s prototypem a experimenty zaměřené na verifikaci mezi danými modely.

The master's thesis introduces the Uppaal tool. It describes the principles and possibilities of modeling and analysis of systems using this tool. It also discusses in more detail the file formats that Uppaal tool uses. The structure of the XML file used to store created systems, the XTR format, which Uppaal uses to store simulation traces, and the IF format, which is necessary to understand the contents of the file in XTR format. The text also mentions available software support for working with these formats. Next part of this master's thesis is about designing user-friendly representation of simulations traces, along with designing application that translates simulation traces into designed representation. At the end of this thesis, the possible continuation of the project is mentioned together with the evaluation of the designed representation and the application.

Les travaux présentés dans ce mémoire s'intéressent aux mécanismes de redondance spécifiés par un protocole de réseau de terrain sur Ethernet. L'objectif est de valider la spécification par rapport à des exigences de disponibilité. Le contexte industriel des travaux nous a amenés à : 1) privilégier une validation par vérification formelle. Le model-checking temporel a été retenu. En effet, le caractère critique des applications industrielles pour lesquelles doit être intégré le protocole impose une vérification exhaustive des propriétés. Les nombreux paramètres temporels permettant de décrire le fonctionnement du protocole nous ont amenés à favoriser une technique prenant en compte le temps. 2) proposer une modélisation par automates temporisés modulaire ainsi qu'une méthode d'instanciation. Celles-ci permettent d'adapter facilement le modèle à vérifier à une architecture de réseau de terrain envisagée lors de la phase d'étude d'une affaire. 3) proposer des abstractions qui favorisent la vérification du modèle par le moteur de model-checking temporel. Les propriétés vérifiées traduisent l'aptitude des mécanismes de redondance à compenser une défaillance du médium ou de l'animation des échanges. Afin d'illustrer la pertinence de ces propositions, la méthode d'instanciation est appliquée à deux architectures et une campagne de vérifications est menée et analysée.

Model-Driven Development is a development approach which is being used frequently in the automotive context in order to design models. EAST-ADL is an architectural language which models systems according to their architectural features, whereas Simulink is a tool environment which models systems according to their behavior. In this thesis work, we propose a set of transformation rules that take into consideration the EAST-ADL architectural model details and the behavioral specifications in Simulink, and generate a formal model, which can be verified UPPAAL model checker. Moreover, we implement these proposed transformation rules in a tool that automates them. The transformation rules proposed in this thesis work would be implemented for every EAST-ADL file with Simulink behavior specifications, generated by the MetaEdit+ tool. Properties like timing constraints, triggering and hierarchy in both EAST-ADL and Simulink have been considered by the transformation rules. Finally, the Brake-by-Wire case study is used to validate the tool and assess the mapping of the elements.

De nombreux systèmes hétérogènes sont complexes et critiques. Ces systèmes intègrent du logiciel et des composants matériels avec des interactions fortes entre ces composants. Dans ce contexte, il est devenu absolument nécessaire de développer des méthodologies et des techniques pour spéciier et valider ces systèmes.Dans l'ingénierie des systèmes, les exigences sont l'expression des besoins qu'un produit spécifique ou un service doit réaliser. Elles sont définies formellement à de nombreuses occasions dans l'ingénierie des systèmes complexes. Dans ce type de système, deux catégories d'exigence sont présentes : les exigences non-fonctionnelles telles que la performance et la fiabilité, les exigences fonctionnelles telles que la vivacité. Pour valider ces exigences, un environnement permettant de simuler et vérifier ces propriétés est essentiel.Dans notre travail, nous proposons une méthodologie basée sur SysML et combinée avec SystemC et Promela/SPIN pour spéciier et valider des systèmes complexes. Cette approche est basée sur l'ingénierie dirigée par les modèles pour premièrement traduire des modèles SysML en SystemC afin de réaliser des simulations et deuxièmement traduire des diagrammes d'état SysML en Promela/SPINain de vérifier des propriétés temporelles extraites des exigences. Cette approche est expérimentée sur une étude de cas pour démontrer sa faisabilité. / Heterogeneous Systems are complex and become very critical. These systems integrate software andhardware components with intensive interaction between them. In this context, there is a strongnecessity to develop methodologies and techniques to specify and validate these systems.In engineering, the requirements are the expression of needs on what a particular product or a serviceshould be or to make. They are used most of the time in a formal sense in the systems engineering.In this kind of systems, several types of requirements are present: non-functional requirements suchas the performance and the reliability and functional requirements such as the liveliness. To validatethese requirements of a system, an environment to simulate and to check the properties is essential.In our work, we propose a methodology based on SysML combined with SystemC and Promela/SPINto specify and validate complex systems. This approach is based on Model Driven Engineeringtechniques to irstly translate SysML models to systemC with the aim of simulation and to mapSysML behavioral diagrams to Promela/SPIN in order to verify temporal properties extracted fromthe requirements. The approach is experimented on case studies to demonstrate its feasibility.