Due to the high electron mobility compared with Si, much attention has been focused on III-V compound semiconductors (gallium arsenide (GaAs) and indium phosphide (InP)) high-speed devices. The high-k material TiO2 not only has high dielectric constant (k = 35-100) but has well lattice match with GaAs and InP substrate. Therefore, titanium oxide (TiO2) was chosen to be the gate oxide in this study. The major problem of III-V compound semiconductors is known to have poor native oxide on it and leading to the Fermi level pinning at the interface of oxide and semiconductor. The C-V stretch-out phenomenon can be observed and the leakage current is high. The higher dielectric constant of poly-crystalline TiO2 film grown on GaAs can be obtained by metal organic chemical vapor deposition (MOCVD). But the high leakage current also occurred due to the grain boundary and defects in the poly-crystalline TiO2 film. The surface passivation of GaAs with (NH4)2Sx treatment (S-GaAs) could prevent it from oxidizing after cleaning and improve the interface properties of MOSFET. The fluorine from liquid phase deposited SiO2 solution can passivate the grain boundary of poly-crystalline MOCVD-TiO2 film and interface state. The high dielectric constant and low leakage current of fluorine passivated MOCVD-TiO2/S-GaAs can be obtained. The leakage current densities are 3.41 x 10-7 A/cm2 and 1.13 x 10-6A/cm2 at ¡Ó1.5 MV/cm, respectively. The Dit is 4.6 x 1011 cm-2eV-1 at the midgap. The dielectric constant can reach 71. In addition, the post-metallization annealing (PMA) is another efficiency way to improve the MOCVD-TiO2 quality. The mechanism of PMA process is from the reaction between the aluminum contact and hydroxyl groups existed on TiO2 film surface. Then the active hydrogen is produced to diffuse through the oxide and passivate the oxide traps. For PMA (350oC)-MOCVD-TiO2 on S-GaAs MOS structure, the leakage current densities can reach 2.5 x 10-7 and 5 x 10-7 A/cm2 at ¡Ó1.5 MV/cm, respectively. The dielectric constant and the Dit are 66 and 5.96 x 1011 cm-2eV-1, respectively. In order to avoid the leakage current from grain boundary of poly-crystalline TiO2, and liquid phase deposited TiO2 (LPD-TiO2) at low temperature can preserve the function of sulfur passivation. Therefore, the amorphous LPD-TiO2 was deposited on S-GaAs. The leakage current densities are 1.04 x 10-7 and 1.91 x 10-7 A/cm2 at ¡Ó0.5 MV/cm, respectively. The Dit is 3.2 x 1011 cm-2eV-1 and the dielectric constant is 48. The LPD-TiO2 film was deposited on (NH4)2Sx treated InP (S-InP), and the 4 x 100 £gm2 enhancement mode N channel InP MOSFET with LPD-TiO2 as gate oxide was fabricated, which showed the good characteristic. The normalized maximum gm is 43 mS/mm at VG = 1.3 V for VDS fixed at 1 V. The maximum calculated £gFE of 348 cm2/V¡Es at VDS = 1 V is obtained.

Texte abrégé et remanié de: Diss.--Philosophische Fakultät--München--Ludwig-Maximilian-Universität, 2001. Titre de soutenance : Forschung, Vernichtung und die Endlösung der Erinnerung : der Prager Jüdische Zentralmuseum ... / Bibliogr. p. 472-498. Index.

Thèse de doctorat--Faculté de missiologie--Rome--Université pontificale grégorienne, 1996. / Bibliogr. p.198-220.

Zugl.: Berlin, Techn. Univ., Diss., 2008. / Hergestellt on demand.

Thesis (M.S.)--West Virginia University, 2003. / Title from document title page. Document formatted into pages; contains x, 87 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 72-73).

Massive multiple-input-multiple-output (MM) is becoming a promising candidate for wireless communications. The idea behind MM is to use a very large number of antennas to increase throughput and energy efficiency by one or more orders of magnitude. In order to make MM feasible, many challenges remain. In the uplink a fundamental question is whether to deploy single massive arrays or to build a virtual array using cooperative base stations. Also, in such large arrays the signal processing involved in receiver combining is non-trivial. Therefore, low complexity receiver designs and deployment scenarios are essential aspects of MM and the thesis mainly focuses on these two areas. In the first part, we investigate three deployment scenarios: (i) a massive co-located array at the cell center; (ii) a massive array clustered at B discrete locations; and (iii) a massive distributed array with a uniform distribution of individual antennae. We also study the effect of propagation parameters, system size, correlation and channel estimation error. We demonstrate by analysis and simulation that in the absence of any system imperfections, a massive distributed array is preferable. However, an intermediate deployment such as a massive array clustered at a few discrete locations can be more practical to implement and more robust to imperfect channel state information. We then focus on the performance of the co-located scenario with different types of antenna array, uniform square and linear arrays. With MM, it may be the case that large numbers of antennas are closely packed to fit in some available space. Hence, channel correlations become important and therefore we investigate the space requirements of different array shapes. In particular, we evaluate the system performance of uniform square and linear arrays by using ergodic capacity and capacity outage. For a range of correlation models, we demonstrate that the uniform square array can yield similar performance to a uniform linear array while providing considerable space saving. In the second part of the thesis we focus on low complexity receiver designs. Due to the high dimension of MM systems there is a considerable interest in detection schemes with a better complexity-performance trade-off. We focus on linear receivers (zero forcing (ZF) and maximum ratio combining (MRC)) used in conjuction with a Vertical Bell Laboratories Layered Space Time (V-BLAST) structure. Our first results show that the performance of MRC V-BLAST approaches that of ZF V-BLAST under a range of imperfect CSI levels, different channel powers and different types of arrays as long as the channel correlations are not too high. Subsequently, we propose novel low complexity receiver designs which maintain the same performance as ZF or ZF V-BLAST. We show that the performance loss of MRC relative to ZF can be removed in certain situations through the use of V-BLAST. The low complexity ordering scheme based on the channel norm (C-V-BLAST) results in a V-BLAST scheme with MRC that has much less complexity than a single ZF linear combiner. An analysis of the SINR at each stage of the V-BLAST approach is also given to support the findings of the proposed technique. We also show that C-V-BLAST remains similar to ZF for more complex adaptive modulation systems and in the presence of channel estimation error, C-V-BLAST can be superior. These results are analytically justified and we derive an exhaustive search algorithm for power control (PC) to bound the potential gains of PC. Using this bound, we demonstrate that C-V-BLAST performs well without the need for additional PC. The final simplification is based on the idea of ordering users based on large scale fading information rather than instantaneous channel knowledge for a V-BLAST scheme with MRC (P-V-BLAST). An explicit closed form analysis for error probability for both co-located and distributed BSs is provided along with a number of novel performance metrics which are useful in designing MM systems. It is shown that the error performance of the distributed scenario can be well approximated by a modified version of a co-located scenario. Another potential advantage of P-V-BLAST is that the ordering can be obtained as soon as the link gains are available. Hence, it is possible that mean SINR values could be used for scheduling and other link control functions. These mean values are solely functions of the link gains and hence, scheduling, power adaptation, rate adaptation, etc. can all be performed more rapidly with P-V-BLAST. Hence, the P-V-BLAST structure may have further advantages beyond a lower complexity compared to C-V-BLAST.

Iron is an essential element for virtually all forms of life. Complicating matters, it is present in the insoluble ferric form in aerobic environments, while the more soluble ferrous form is found in anaerobic or reducing environments. Vibrio cholerae, the causative agent of the disease cholera, requires iron to survive. In order to meet the need for iron, V. cholerae expresses a variety of iron acquisition systems. One of these systems, Feo, is highly conserved among bacterial species as well as archaea and transports ferrous iron. The Feo system consists of three proteins: FeoA, FeoB, and FeoC. Previous work using the bacterial adenylate cyclase two hybrid system has shown that FeoC interacts with the cytoplasmic N-terminal domain of FeoB. However, the significance of this interaction is not known. In this study, V. cholerae Feo system proteins were analyzed for residues important for the interaction between FeoB and FeoC. In addition, FeoA and FeoC were purified for antibody production. It was found that a residue in the G protein domain of FeoB was not necessary for interaction with FeoC. However, a conserved residue in FeoC did abolish the interaction with FeoB. These results indicate that there is at least one residue important in the interaction of FeoB and FeoC, although further characterization will most likely reveal more. Antibodies to FeoA and FeoC were generated to use them for further characterization of the Feo system. / text

In the past few decades, Si-based CMOS technology is approaching to its physical quantum limit by scaling down the gate length and gate oxide thickness to achieve higher drive current for low power and high speed application. High k/III-V stack provides an alternative solution because III-V based metal-oxide-semiconductor (MOS) devices have higher drive current due to the higher electron mobility than silicon. Also high k oxides lower the gate leakage current significantly due to larger thickness under the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. The main obstacle for high k/III-V based MOSFETs is the lack of high quality, thermodynamically stable insulators that passivate the interface, which is also the main driving force in the research area of high k/III-V stack. One of the main focuses of this dissertation is developing a fabrication process flow to lower the interface trap density to enhance the performance of MOSFETs with high k oxides on III-V substrates. Also, an emerging memory device with SiO[subscript x] is also developed. This device can be electrically switched between a high-resistance state (HRS, or OFF-state) and a low-resistance state (LRS, or ON-state). Also it shows high potential for next generation nonvolatile memories due to its small cell area, fast write/erase time, low write voltage, good endurance and scalability. The other main focuses of this dissertation is studying the electroforming, set/reset voltages and passivation issue in this resistive random access memory (RRAM or ReRAM). The first part of this dissertation is about lowering the interface trap density of high k/III-V stack by using a thin layer of Al₂O₃ or LaAlO₃. ALD Al₂O₃/HfO₂ bi-layer gate oxide with different Al₂O₃ thickness (0, 5, 10Å) was deposited. Also ALD LaAlO₃/HfO₂ bi-layer gate oxide with different LaAlO₃ thickness (0, 5, 10, 20, 30, 42Å) was deposited. The total EOT of the bi-layer was maintained at ~1.8nm. Also single La[subscript x]Al[subscript 1-X]O (X =0.25, 0.33, 0.5, 0.66, 0.75) gate dielectric with different La doping level was deposited (EOT=2.5±0.4nm). Device characteristics are compared by using different thickness of interfacial layer. The second part of this dissertation is about F incorporation into high k oxide by using SF₆ plasma. The effect of SF₆ plasma treatment of HfO₂ on III-V substrates is demonstrated. Also effect of different plasma power and different treatment time of SF₆ plasma is studied to optimize plasma conditions. High k bilayer (Al₂O₃/HfO₂) is also used to further improve the device performance by better interface passivation with Al₂O₃. HfO₂ gate oxide dielectric is also engineered using SF₆ plasma treatment to incorporate more F. The third part is a study of III-V tunneling FET using In[subscript 0.7]Ga[subscript 0.3]As p-n junction. The device performance with different n doping concentration is compared. Higher n doping concentration will increase the drive current by reducing the tunneling width while too higher n doping concentration results in tunneling in the middle of p-n junction and significantly increase the subthreshold swing. The forth part is the electroforming, set/reset and passivation study of ReRAM device with SiO[subscript x]. Different methods to reduce the electroforming voltage are developed. Set/reset process is also studied and a possible model is proposed to explain the set/ reset process. A new device structure without sidewall edge is studied for passivation and application in air. The final part is the summary of Ph.D work and also suggestions for future work are discussed. / text

Continuous downscaling of transistor size has been the major trend of the semiconductor industry for the past half century. In recent years, however, fundamental physical limits to continued downscaling were encountered. In order to overcome these limits, the industry experimented --- and continues to experiment --- with many new materials and architectures. Non-invasive, in-line methods of characterizing critical properties of these structures are in demand. This dissertation develops optical second-harmonic generation (SHG) to characterize performance-limiting defects, band alignment or strain distribution in four advanced electronic material systems of current interest: (1) Hot carrier injection (HCI) is a key determinant of the reliability of ultrathin silicon-on-insulator (SOI) devices. We show that time-dependent electrostatic-field-induced SHG probes HCI from SOI films into both native and buried oxides without device fabrication. (2) Band offsets between advanced high-k gate dielectrics and their substrates govern performance-limiting leakage currents, and elucidate interfacial bond structure. We evaluate band offsets of as-deposited and annealed Al₂O₃, HfO₂ and BeO films with Si using internal photoemission techniques. (3) Epi-GaAs films grown on Si combine the high carrier mobility and superior optical properties of III-V semiconductors with the established Si platform, but are susceptible to formation of anti-phase boundary (APB) defects. We show that SHG in reflection from APB-laden epi-films is dramatically weaker than from control layers without APBs. Moreover, scanning SHG images of APB-rich layers reveal microstructure lacking in APB-free layers. These findings are attributed to the reversal in sign of the second-order nonlinear optical susceptibility [chi]⁽²⁾ between neighboring anti-phase domains, and demonstrate that SHG characterizes APBs sensitively, selectively and non-invasively. (4) 3D integration --- i.e. connecting vertically stacked chips with metal through-Si-vias (TSVs) --- is an important new approach for improving performance at the inter-chip level, but thermal stress of the TSVs on surrounding Si can compromise reliability. We present scanning SHG images for different polarization combinations and azimuthal orientations that reveal the sensitivity of SHG to strain fields surrounding TSVs. Taken together, these results demonstrate that SHG can identify performance-limiting defects and important material properties quickly and non-invasively for advanced MOSFET device applications. / text

Not available