Les processus décisionnels de Markov (MDPs) modélisent des problèmes de décisionsséquentielles dans lesquels un utilisateur interagit avec l’environnement et adapte soncomportement en prenant en compte les signaux de récompense numérique reçus. La solutiond’unMDP se ramène à formuler le comportement de l’utilisateur dans l’environnementà l’aide d’une fonction de politique qui spécifie quelle action choisir dans chaque situation.Dans de nombreux problèmes de décision du monde réel, les utilisateurs ont despréférences différentes, donc, les gains de leurs actions sur les états sont différents et devraientêtre re-décodés pour chaque utilisateur. Dans cette thèse, nous nous intéressonsà la résolution des MDPs pour les utilisateurs ayant des préférences différentes.Nous utilisons un modèle nommé MDP à Valeur vectorielle (VMDP) avec des récompensesvectorielles. Nous proposons un algorithme de recherche-propagation qui permetd’attribuer une fonction de valeur vectorielle à chaque politique et de caractériser chaqueutilisateur par un vecteur de préférences sur l’ensemble des fonctions de valeur, où levecteur de préférence satisfait les priorités de l’utilisateur. Etant donné que le vecteurde préférences d’utilisateur n’est pas connu, nous présentons plusieurs méthodes pourrésoudre des MDP tout en approximant le vecteur de préférence de l’utilisateur.Nous introduisons deux algorithmes qui réduisent le nombre de requêtes nécessairespour trouver la politique optimale d’un utilisateur: 1) Un algorithme de recherchepropagation,où nous propageons un ensemble de politiques optimales possibles pourle MDP donné sans connaître les préférences de l’utilisateur. 2) Un algorithme interactifd’itération de la valeur (IVI) sur les MDPs, nommé algorithme d’itération de la valeurbasé sur les avantages (ABVI) qui utilise le clustering et le regroupement des avantages.Nous montrons également comment l’algorithme ABVI fonctionne correctement pourdeux types d’utilisateurs différents: confiant et incertain.Nous travaillons finalement sur une méthode d’approximation par critére de regret minimaxcomme méthode pour trouver la politique optimale tenant compte des informationslimitées sur les préférences de l’utilisateur. Dans ce système, tous les objectifs possiblessont simplement bornés entre deux limites supérieure et inférieure tandis que le systèmeine connaît pas les préférences de l’utilisateur parmi ceux-ci. Nous proposons une méthodeheuristique d’approximation par critère de regret minimax pour résoudre des MDPsavec des récompenses inconnues. Cette méthode est plus rapide et moins complexe queles méthodes existantes dans la littérature. / Markov decision processes (MDPs) are models for solving sequential decision problemswhere a user interacts with the environment and adapts her policy by taking numericalreward signals into account. The solution of an MDP reduces to formulate the userbehavior in the environment with a policy function that specifies which action to choose ineach situation. In many real world decision problems, the users have various preferences,and therefore, the gain of actions on states are different and should be re-decoded foreach user. In this dissertation, we are interested in solving MDPs for users with differentpreferences.We use a model named Vector-valued MDP (VMDP) with vector rewards. We propose apropagation-search algorithm that allows to assign a vector-value function to each policyand identify each user with a preference vector on the existing set of preferences wherethe preference vector satisfies the user priorities. Since the user preference vector is notknown we present several methods for solving VMDPs while approximating the user’spreference vector.We introduce two algorithms that reduce the number of queries needed to find the optimalpolicy of a user: 1) A propagation-search algorithm, where we propagate a setof possible optimal policies for the given MDP without knowing the user’s preferences.2) An interactive value iteration algorithm (IVI) on VMDPs, namely Advantage-basedValue Iteration (ABVI) algorithm that uses clustering and regrouping advantages. Wealso demonstrate how ABVI algorithm works properly for two different types of users:confident and uncertain.We finally work on a minimax regret approximation method as a method for findingthe optimal policy w.r.t the limited information about user’s preferences. All possibleobjectives in the system are just bounded between two higher and lower bounds while thesystem is not aware of user’s preferences among them. We propose an heuristic minimaxregret approximation method for solving MDPs with unknown rewards that is faster andless complex than the existing methods in the literature.

Desde a década de 60, o aprimoramento das técnicas de fabricação de circuitos integrados que usam lógica binária tem levado ao aumento exponencial na densidade de dispositivos, melhoria do desempenho, redução da energia consumida e redução dos custos de fabricação dos circuitos integrados no estado da arte. Esse avanço tem sido alcançado historicamente pela miniaturização dos dispositivos que, já em escala nanométrica, começam a encontrar limites físicos para a sua redução. Com o intuito de dar continuidade ao avanço tecnológico, muitos trabalhos têm proposto a compactação da informação através do uso de lógica não binária como solução alternativa para a melhoria de desempenho de circuitos no estado da arte. Nesse sentido, diversos trabalhos foram desenvolvidos em diferentes tecnologias que vão de circuitos bipolares a dispositivos quânticos, entretanto, até o presente momento, nenhuma tecnologia demonstrou ao mesmo tempo os requisitos de desempenho, consumo, área e confiabilidade, necessários à aplicação em circuitos de alta escala de integração. Este trabalho apresenta uma nova família de circuitos de lógica quaternária com alto desempenho, baixos consumo e área e que usa tecnologia CMOS. Os circuitos desenvolvidos neste trabalho fazem uso de três fontes de alimentação e até oito diferentes transistores com diferentes tensões de limiar para realizar a lógica quaternária. São apresentados circuitos elementares como inversores e circuitos literais e com eles construídos circuitos aritméticos e multiplexadores. Os circuitos são simulados com a ferramenta SPICE usando a tecnologia TSMC 0,18 μm e os resultados são comparados com circuitos equivalentes em lógica binária. Na comparação de um somador completo quaternário de quatro bits, por exemplo, com o circuito equivalente em lógica binária, a implementação quaternária apresenta melhoria 55% na velocidade, 63% no consumo de potência e utiliza pouco mais de duas vezes o número de transistores. Este trabalho também propõe o uso de lógica quaternária em FPGA e são desenvolvidos blocos lógicos programáveis quaternários. Resultados de mapeamento lógico de circuitos aritméticos em blocos lógicos programáveis apresentam grande redução em área e consumo de potência na implementação quaternária quando comparado aos equivalentes binários. Em alguns circuitos quaternários, o consumo de potência e o número de transistores usados são reduzidos a 3% do consumo e do número de transistores usados nos circuitos equivalentes binários, enquanto o atraso crítico é duas vezes maior do que o atraso crítico binário. / Since the decade of 60, the improvement of techniques for manufacturing integrated circuits that use binary logic has led to the exponential increase in the density of devices, improving performance, reducing energy consumption and reducing costs of manufacture of integrated circuits in the state of the art. This breakthrough has been achieved historically by the miniaturization of devices, already in nano, starting to reach physical limits to their reduction. In order to give continuity to technological advancement, many studies have proposed the compaction of information through the use of non-binary logic as an alternative for the performance improvement of the state of the art circuits. Accordingly, several studies have been developed in different technologies ranging from bipolar circuits to quantum devices, however, at the moment, no technology demonstrated at the same time the performance requirements, consumption, area and reliability necessary for the application in very large scale of integration. This paper presents a new family of quaternary logic circuits with high performance, low consumption and area, which uses CMOS technology. The circuits developed in this work make use of three power supplies and up to eight different transistors with different threshold voltages, to perform the quaternary logic. Elementary circuits such as inverters and literal circuits are presented and used to implement multiplexers and arithmetic circuits. The circuits are simulated with the SPICE tool using TSMC 0.18 μm technology and the results are compared with equivalent circuits in binary logic. Comparison of a quaternary full adder of four bits, for example, with the equivalent circuit in binary logic shows 55% improvement in speed and 63% in the power consumption for the quaternary implementation and it uses little more than twice the number of transistors. This paper also proposes the use of quaternary logic in FPGA and quaternary configurable logic blocks are developed. Logical mapping results of arithmetic circuits in configurable logic blocks show great reduction in area and power consumption of the quaternary implementation compared to the equivalent binary. In some quaternary circuits, the consumption of power and the number of transistors used are reduced to 3% of consumption and the number of transistors used in the binary equivalent circuits, while the critical delay is two times higher than the binary critical delay.

Orientador: Maria Sueli Marconi Roversi / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Matematica, Estatistica e Computação Cientifica / Made available in DSpace on 2018-08-04T02:57:42Z (GMT). No. of bitstreams: 1 Piccoli_Bibiana_M.pdf: 1524742 bytes, checksum: 4328a3e766798f219a0267cdf6e892b7 (MD5) Previous issue date: 2005 / Resumo: Estudamos um tipo especial de função denominada função ponto a conjunto, que associa a cada elemento de um espaço métrico um único subconjunto não vazio de outro espaço métrico. A noção de continuidade das funções usuais caracterizada por propriedades equivalentes, enun-ciadas em termos de vizinhanças ou em termos de seqüências, deram origem a versões corres-pondentes para as funções ponto a conjunto. As propriedades adaptadas, não mais equivalentes, são conhecidas como semicontinuidade superior e semicontinuidade inferior, respectivamente. Uma condição do tipo Lipschitz e um tipo de continuidade propriamente, obtido munindo-se o contradomínio da métrica de Hausdorff, foram relacionados à semicontinuidade. Algumas propriedades algébricas ou topológicas dos conjuntos imagem foram essenciais para os resulta-dos obtidos. Abordamos adaptações de alguns resultados clássicos da análise funcional como os teoremas da limitação uniforme, da aplicação aberta e do gráfico fechado para as funções ponto a conjunto caracterizadas como processos convexos, que são os análogos dos operadores lineares. Estabelecemos também uma versão do teorema de Schauder sobre pontos fixos para funções ponto a conjunto e também para as do tipo contração / Abstract: We study a mapping called a set-valued map which associates with each point of a metric space a non empty subset of another metric space. In the case of single-valued maps, contin-uous functions are characterized by two equivalent properties: one in terms of neighborhood and other in terms of sequences. These two properties can be adapted to the case of set-valued maps, are no longer equivalent and are called upper semi continuity and lower semi continuity, respectively. We adapt to the set-valued case the concept of Lipschitz applications and also a type of continuity when the range is enjoyed with the Hausdorff metric. We related them with the conditions of semi continuity. Some of the results depends on algebraic or topological prop-erties of the images. We adapt to closed convex process the principIe of uniform boundedness, the Banach open mapping and closed graph theorems. The closed convex processes are the set-valued analogues of continuous linear operators. We also establish two fixed point result for set-valued maps: the first generalizes the Schauder fixed point theorem and the second considers that of contraction type / Mestrado / Matematica / Mestre em Matemática

No description available.

The relationship between the convergence of a sequence of self mappings of a metric space and their fixed points, known as the stability (or continuity) of fixed points has been of continuing interest and widely studied in fixed point theory. In this thesis we study the stability of common fixed points in a Hausdorff uniform space whose uniformity is generated by a family of pseudometrics, by using some general notations of convergence. These results are then extended to 2-metric spaces due to S. Gähler. In addition, a well-known theorem of T. Suzuki that generalized the Banach Contraction Principle is also extended to 2-metric spaces and applied to obtain a coincidence theorem for a pair of mappings on an arbitrary set with values in a 2-metric space. Further, we prove the existence of coincidence and fixed points of Ćirić type weakly generalized contractions in metric spaces. Subsequently, the above result is utilized to discuss applications to the convergence of modified Mann and Ishikawa iterations in a convex metric space. Finally, we obtain coincidence, fixed and stationary point results for multi-valued and hybrid pairs of mappings on a metric space.

Orientador: Alberto Martins Jorge / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-07T17:31:45Z (GMT). No. of bitstreams: 1 Bertone_OsvaldoHugo_M.pdf: 1638189 bytes, checksum: de96158c2363994f79a61d1d7ce1e9aa (MD5) Previous issue date: 2005 / Resumo: Neste trabalho é proposto um Registrador Cíclico para circuitos MVL (Multi-valued Logic) utilizando transistores NMOS e PMOS para uma configuração de quatro níveis lógicos. Este circuito usa certas características secundárias (normalmente indesejadas) dos transistores MOS. Uma particularidade deste registrador são os níveis lógicos auto-definidos com uma alta precisão. Isto permite incrementar a Lógica para mais valores, não estando limitada somente a Lógica Ternária ou Quaternária (as mais usadas em circuitos MVLs), seu uso pode ser estendido para Decimal, Hexadecimal ou mais. O Registrador Cíclico proposto, alem de armazenar um dado multi-valor com um nível de tensão preciso, ainda, fornece a saída com qualquer possível deslocamento lógico sem degradação da precisão. Este registrador permitirá o desenvolvimento de circuitos lógicos como contadores, toggle switches, shift registers, flip-flops em vários níveis, deslocamentos de valores (negação de Post), conversores D/A e A/D, etc¿ Algumas vantagens que este circuito oferece é sua alta resposta em freqüência e sua pouca dependência dos parâmetros do transistor, alcançando uma robustez comparável com os circuitos binários. Como uma aplicação deste registrador proposto é apresentado um Multiplicador Quaternário e comparado com um Multiplicador Binário utilizando a mesma tecnologia. Neste texto serão desenvolvidos os circuitos e simulados no OrCad (PSpice [01]) utilizando um modelo de transistor NMOS e outro PMOS fornecidos pela foundry AMS (Austria Micro Systems) descritos no Apêndice I. O Registrador Cíclico para circuitos MVL foi apresentado pelo autor no Congresso SUCESU 2005 no dia 31 de março de 2005 em Belo Horizonte, MG, Brasil / Abstract: The Cyclical Register for MVL circuits (Multi-valued Logic) proposed is composed by NMOS and PMOS Transistors. This circuit uses the advantage of certain secondary characteristics (normally undesirable) of the MOS transistors. One peculiarity of this register is that the logical levels are defined by itself with a very high precision ; this, permits to increase the logic to many values. Since it is not limited to ternary or quaternary logic (more used MVLs), its use can be extended to decimal, hexadecimal and others. The proposed cyclical register, besides storing the multi-value data with precise voltage level, still, supplies the output with any possible logical shift without the degradation of precision. This register will allow the development of logical circuits as counter, toggle switch, shift register, flip-flop in several levels, shift of value, D/A and A/D converter, etc¿ Some advantages that this circuit offers is its high frequency response and its minor dependency of the parameter of the transistors, providing a robustness comparable to the current binary circuits. As an application of this proposed Register a Quaternary Multiplier is presented and compared with the Binary Multiplier with the same technology. On this paper the circuits will be developed and simulated in the OrCad (Pspice [01]), using the transistors models NMOS and PMOS supplied by foundry AMS (Austria Micro Systems) detailed in the Appendix I. The Cyclical Register for MVL circuits was presented by the author in the Congress SUCESU 2005 in March 31st, 2005 in Belo Horizonte, MG, Brazil / Mestrado / Microeletronica / Mestre em Engenharia Elétrica

京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第22587号 / 情博第724号 / 新制||情||124(附属図書館) / 京都大学大学院情報学研究科システム科学専攻 / (主査)教授 下平 英寿, 教授 田中 利幸, 教授 山下 信雄, 教授 林 和則(大阪市立大学) / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

京都大学 / 新制・課程博士 / 博士(理学) / 甲第23402号 / 理博第4737号 / 新制||理||1679(附属図書館) / 京都大学大学院理学研究科数学・数理解析専攻 / (主査)准教授 照井 一成, 教授 牧野 和久, 教授 長谷川 真人 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DGAM

The ring of real-valued continuous functions on a completely regular frame L is denoted by RL. As usual, βL denotes the Stone-Cech compactification of ˇ L. In the thesis we study ideals of RL induced by sublocales of βL. We revisit the notion of purity in this ring and use it to characterize basically disconnected frames. The socle of the ring RL is characterized as an ideal induced by the sublocale of βL which is the join of all nowhere dense sublocales of βL. A localic map f : L → M induces a ring homomorphism Rh: RM → RL by composition, where h: M → L is the left adjoint of f. We explore how the sublocale-induced ideals travel along the ring homomorphism Rh, to and fro, via expansion and contraction, respectively. The socle of a ring is the sum of its minimal ideals. In the literature, the socle of RL has been characterized in terms of atoms. Since atoms do not always exist in frames, it is better to express the socle in terms of entities that exist in every frame. In the thesis we characterize the socle as one of the types of ideals induced by sublocales. A classical operator invented by Gillman, Henriksen and Jerison in 1954 is used to create a homomorphism of quantales. The frames in which every cozero element is complemented (they are called P-frames) are characterized in terms of some properties of this quantale homomorphism. Also characterized within the category of quantales are localic analogues of the continuous maps of R.G. Woods that characterize normality in the category of Tychonoff spaces. / Mathematical Sciences / Ph. D. (Mathematics)

‘If-then’ rule sets are one of the most expressive and human-readable knowledge representations. This thesis deals with optimization and analysis of decision and inhibitory rules for decision tables with many-valued decisions. The most important areas of applications are knowledge extraction and representation. The benefit of considering inhibitory rules is connected with the fact that in some situations they can describe more knowledge than the decision ones. Decision tables with many-valued decisions arise in combinatorial optimization, computational geometry, fault diagnosis, and especially under the processing of data sets. In this thesis, various examples of real-life problems are considered which help to understand the motivation of the investigation. We extend relatively simple results obtained earlier for decision rules over decision tables with many-valued decisions to the case of inhibitory rules. The behavior of Shannon functions (which characterize complexity of rule systems) is studied for finite and infinite information systems, for global and local approaches, and for decision and inhibitory rules. The extensions of dynamic programming for the study of decision rules over decision tables with single-valued decisions are generalized to the case of decision tables with many-valued decisions. These results are also extended to the case of inhibitory rules. As a result, we have algorithms (i) for multi-stage optimization of rules relative to such criteria as length or coverage, (ii) for counting the number of optimal rules, (iii) for construction of Pareto optimal points for bi-criteria optimization problems, (iv) for construction of graphs describing relationships between two cost functions, and (v) for construction of graphs describing relationships between cost and accuracy of rules. The applications of created tools include comparison (based on information about Pareto optimal points) of greedy heuristics for bi-criteria optimization of rules, and construction (based on multi-stage optimization of rules) of relatively short systems of rules that can be used for knowledge representation.