Nuel Belnap schlug 1977 eine vierwertige Logik vor, die -- im Gegensatz zur klassischen Logik -- die Faehigkeit haben sollte, sowohl mit widerspruechlicher als auch mit fehlender Information umzugehen. Diese Logik hat jedoch den Nachteil, dass sie Saetze der Form "wenn ..., dann ..." nicht ausdruecken kann. Ausgehend von dieser Beobachtung analysieren wir die beiden nichtklassischen Aspekte, Widerspruechlichkeit und fehlende Information, indem wir eine dreiwertige Logik entwickeln, die mit widerspruechlicher Information umgehen kann und eine Modallogik, die mit fehlender Information umgehen kann. Beide Logiken sind nicht monoton. Wir untersuchen Eigenschaften, wie z.B. Kompaktheit, Entscheidbarkeit, Deduktionstheoreme und Berechnungkomplexitaet dieser Logiken. Es stellt sich heraus, dass die dreiwertige Logik, nicht kompakt und ihre Folgerungsmenge im Allgemeinen nicht rekursiv aufzaehlbar ist. Beschraenkt man sich hingegen auf endliche Formelmengen, so ist die Folgerungsmenge rekursiv entscheidbar, liegt in der Klasse $\Sigma_2^P$ der polynomiellen Zeithierarchie und ist DIFFP-schwer. Wir geben ein auf semantischen Tableaux basierendes, korrektes und vollstaendiges Berechnungsverfahren fuer endliche Praemissenmengen an. Darueberhinaus untersuchen wir Abschwaechungen der Kompaktheitseigenschaft. Die nichtmonotone auf S5-Modellen basierende Modallogik stellt sich als nicht minder komplex heraus. Auch hier untersuchen wir eine sinnvolle Abschwaechung der Kompaktheitseigenschaft. Desweiteren studieren wir den Zusammenhang zu anderen nichtmonotonen Modallogiken wie Moores autoepistemischer Logik (AEL) und McDermotts NML-2. Wir zeigen, dass unsere Logik zwischen AEL und NML-2 liegt. Schliesslich koppeln wir die entworfene Modallogik mit der dreiwertigen Logik. Die dabei enstehende Logik MKT ist eine Erweiterung des nichtmonotonen Fragments von Belnaps Logik. Wir schliessen unsere Betrachtungen mit einem Vergleich von MKT und verschiedenen informationstheoretischen Logiken, wie z.B. Nelsons N und Heytings intuitionistischer Logik ab.

京都大学 / 新制・課程博士 / 博士(理学) / 甲第23676号 / 理博第4766号 / 新制||理||1683(附属図書館) / 京都大学大学院理学研究科数学・数理解析専攻 / (主査)教授 森脇 淳, 教授 雪江 明彦, 教授 吉川 謙一 / 学位規則第4条第1項該当 / Doctor of Science / Kyoto University / DFAM

The results of this thesis are motivated by the investigation of abstract Cauchy problems. Our primary contribution is encapsulated in two new theorems. The first main theorem is a generalisation of a result of E. M. Stein. In particular, we show that every symmetric diffusion semigroup acting on a complex-valued Lebesgue space has a tensor product extension to a UMD-valued Lebesgue space that can be continued analytically to sectors of the complex plane. Moreover, this analytic continuation exhibits pointwise convergence almost everywhere. Both conclusions hold provided that the UMD space satisfies a geometric condition that is weak enough to include many classical spaces. The theorem is proved by showing that every symmetric diffusion semigroup is dominated by a positive symmetric diffusion semigoup. This allows us to obtain (a) the existence of the semigroup's tensor extension, (b) a vector-valued version of the Hopf--Dunford--Schwartz ergodic theorem and (c) an holomorphic functional calculus for the extension's generator. The ergodic theorem is used to prove a vector-valued version of a maximal theorem by Stein, which, when combined with the functional calculus, proves the pointwise convergence theorem. The second part of the thesis proves the existence of abstract Strichartz estimates for any evolution family of operators that satisfies an abstract energy and dispersive estimate. Some of these Strichartz estimates were already announced, without proof, by M. Keel and T. Tao. Those estimates which are not included in their result are new, and are an abstract extension of inhomogeneous estimates recently obtained by D. Foschi. When applied to physical problems, our abstract estimates give new inhomogeneous Strichartz estimates for the wave equation, extend the range of inhomogeneous estimates obtained by M. Nakamura and T. Ozawa for a class of Klein--Gordon equations, and recover the inhomogeneous estimates for the Schr??dinger equation obtained independently by Foschi and M. Vilela. These abstract estimates are applicable to a range of other problems, such as the Schr??dinger equation with a certain class of potentials.

Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (p. 87-91).

Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (p. 85-91).

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This study focuses on improving the quality of statistical speech synthesis based on sinusoidal models. Vocoders play a crucial role during the parametrisation and reconstruction process, so we first lead an experimental comparison of a broad range of the leading vocoder types. Although our study shows that for analysis / synthesis, sinusoidal models with complex amplitudes can generate high quality of speech compared with source-filter ones, component sinusoids are correlated with each other, and the number of parameters is also high and varies in each frame, which constrains its application for statistical speech synthesis. Therefore, we first propose a perceptually based dynamic sinusoidal model (PDM) to decrease and fix the number of components typically used in the standard sinusoidal model. Then, in order to apply the proposed vocoder with an HMM-based speech synthesis system (HTS), two strategies for modelling sinusoidal parameters have been compared. In the first method (DIR parameterisation), features extracted from the fixed- and low-dimensional PDM are statistically modelled directly. In the second method (INT parameterisation), we convert both static amplitude and dynamic slope from all the harmonics of a signal, which we term the Harmonic Dynamic Model (HDM), to intermediate parameters (regularised cepstral coefficients (RDC)) for modelling. Our results show that HDM with intermediate parameters can generate comparable quality to STRAIGHT. As correlations between features in the dynamic model cannot be modelled satisfactorily by a typical HMM-based system with diagonal covariance, we have applied and tested a deep neural network (DNN) for modelling features from these two methods. To fully exploit DNN capabilities, we investigate ways to combine INT and DIR at the level of both DNN modelling and waveform generation. For DNN training, we propose to use multi-task learning to model cepstra (from INT) and log amplitudes (from DIR) as primary and secondary tasks. We conclude from our results that sinusoidal models are indeed highly suited for statistical parametric synthesis. The proposed method outperforms the state-of-the-art STRAIGHT-based equivalent when used in conjunction with DNNs. To further improve the voice quality, phase features generated from the proposed vocoder also need to be parameterised and integrated into statistical modelling. Here, an alternative statistical model referred to as the complex-valued neural network (CVNN), which treats complex coefficients as a whole, is proposed to model complex amplitude explicitly. A complex-valued back-propagation algorithm using a logarithmic minimisation criterion which includes both amplitude and phase errors is used as a learning rule. Three parameterisation methods are studied for mapping text to acoustic features: RDC / real-valued log amplitude, complex-valued amplitude with minimum phase and complex-valued amplitude with mixed phase. Our results show the potential of using CVNNs for modelling both real and complex-valued acoustic features. Overall, this thesis has established competitive alternative vocoders for speech parametrisation and reconstruction. The utilisation of proposed vocoders on various acoustic models (HMM / DNN / CVNN) clearly demonstrates that it is compelling to apply them for the parametric statistical speech synthesis.

Desde a década de 60, o aprimoramento das técnicas de fabricação de circuitos integrados que usam lógica binária tem levado ao aumento exponencial na densidade de dispositivos, melhoria do desempenho, redução da energia consumida e redução dos custos de fabricação dos circuitos integrados no estado da arte. Esse avanço tem sido alcançado historicamente pela miniaturização dos dispositivos que, já em escala nanométrica, começam a encontrar limites físicos para a sua redução. Com o intuito de dar continuidade ao avanço tecnológico, muitos trabalhos têm proposto a compactação da informação através do uso de lógica não binária como solução alternativa para a melhoria de desempenho de circuitos no estado da arte. Nesse sentido, diversos trabalhos foram desenvolvidos em diferentes tecnologias que vão de circuitos bipolares a dispositivos quânticos, entretanto, até o presente momento, nenhuma tecnologia demonstrou ao mesmo tempo os requisitos de desempenho, consumo, área e confiabilidade, necessários à aplicação em circuitos de alta escala de integração. Este trabalho apresenta uma nova família de circuitos de lógica quaternária com alto desempenho, baixos consumo e área e que usa tecnologia CMOS. Os circuitos desenvolvidos neste trabalho fazem uso de três fontes de alimentação e até oito diferentes transistores com diferentes tensões de limiar para realizar a lógica quaternária. São apresentados circuitos elementares como inversores e circuitos literais e com eles construídos circuitos aritméticos e multiplexadores. Os circuitos são simulados com a ferramenta SPICE usando a tecnologia TSMC 0,18 μm e os resultados são comparados com circuitos equivalentes em lógica binária. Na comparação de um somador completo quaternário de quatro bits, por exemplo, com o circuito equivalente em lógica binária, a implementação quaternária apresenta melhoria 55% na velocidade, 63% no consumo de potência e utiliza pouco mais de duas vezes o número de transistores. Este trabalho também propõe o uso de lógica quaternária em FPGA e são desenvolvidos blocos lógicos programáveis quaternários. Resultados de mapeamento lógico de circuitos aritméticos em blocos lógicos programáveis apresentam grande redução em área e consumo de potência na implementação quaternária quando comparado aos equivalentes binários. Em alguns circuitos quaternários, o consumo de potência e o número de transistores usados são reduzidos a 3% do consumo e do número de transistores usados nos circuitos equivalentes binários, enquanto o atraso crítico é duas vezes maior do que o atraso crítico binário. / Since the decade of 60, the improvement of techniques for manufacturing integrated circuits that use binary logic has led to the exponential increase in the density of devices, improving performance, reducing energy consumption and reducing costs of manufacture of integrated circuits in the state of the art. This breakthrough has been achieved historically by the miniaturization of devices, already in nano, starting to reach physical limits to their reduction. In order to give continuity to technological advancement, many studies have proposed the compaction of information through the use of non-binary logic as an alternative for the performance improvement of the state of the art circuits. Accordingly, several studies have been developed in different technologies ranging from bipolar circuits to quantum devices, however, at the moment, no technology demonstrated at the same time the performance requirements, consumption, area and reliability necessary for the application in very large scale of integration. This paper presents a new family of quaternary logic circuits with high performance, low consumption and area, which uses CMOS technology. The circuits developed in this work make use of three power supplies and up to eight different transistors with different threshold voltages, to perform the quaternary logic. Elementary circuits such as inverters and literal circuits are presented and used to implement multiplexers and arithmetic circuits. The circuits are simulated with the SPICE tool using TSMC 0.18 μm technology and the results are compared with equivalent circuits in binary logic. Comparison of a quaternary full adder of four bits, for example, with the equivalent circuit in binary logic shows 55% improvement in speed and 63% in the power consumption for the quaternary implementation and it uses little more than twice the number of transistors. This paper also proposes the use of quaternary logic in FPGA and quaternary configurable logic blocks are developed. Logical mapping results of arithmetic circuits in configurable logic blocks show great reduction in area and power consumption of the quaternary implementation compared to the equivalent binary. In some quaternary circuits, the consumption of power and the number of transistors used are reduced to 3% of consumption and the number of transistors used in the binary equivalent circuits, while the critical delay is two times higher than the binary critical delay.

Desde a década de 60, o aprimoramento das técnicas de fabricação de circuitos integrados que usam lógica binária tem levado ao aumento exponencial na densidade de dispositivos, melhoria do desempenho, redução da energia consumida e redução dos custos de fabricação dos circuitos integrados no estado da arte. Esse avanço tem sido alcançado historicamente pela miniaturização dos dispositivos que, já em escala nanométrica, começam a encontrar limites físicos para a sua redução. Com o intuito de dar continuidade ao avanço tecnológico, muitos trabalhos têm proposto a compactação da informação através do uso de lógica não binária como solução alternativa para a melhoria de desempenho de circuitos no estado da arte. Nesse sentido, diversos trabalhos foram desenvolvidos em diferentes tecnologias que vão de circuitos bipolares a dispositivos quânticos, entretanto, até o presente momento, nenhuma tecnologia demonstrou ao mesmo tempo os requisitos de desempenho, consumo, área e confiabilidade, necessários à aplicação em circuitos de alta escala de integração. Este trabalho apresenta uma nova família de circuitos de lógica quaternária com alto desempenho, baixos consumo e área e que usa tecnologia CMOS. Os circuitos desenvolvidos neste trabalho fazem uso de três fontes de alimentação e até oito diferentes transistores com diferentes tensões de limiar para realizar a lógica quaternária. São apresentados circuitos elementares como inversores e circuitos literais e com eles construídos circuitos aritméticos e multiplexadores. Os circuitos são simulados com a ferramenta SPICE usando a tecnologia TSMC 0,18 μm e os resultados são comparados com circuitos equivalentes em lógica binária. Na comparação de um somador completo quaternário de quatro bits, por exemplo, com o circuito equivalente em lógica binária, a implementação quaternária apresenta melhoria 55% na velocidade, 63% no consumo de potência e utiliza pouco mais de duas vezes o número de transistores. Este trabalho também propõe o uso de lógica quaternária em FPGA e são desenvolvidos blocos lógicos programáveis quaternários. Resultados de mapeamento lógico de circuitos aritméticos em blocos lógicos programáveis apresentam grande redução em área e consumo de potência na implementação quaternária quando comparado aos equivalentes binários. Em alguns circuitos quaternários, o consumo de potência e o número de transistores usados são reduzidos a 3% do consumo e do número de transistores usados nos circuitos equivalentes binários, enquanto o atraso crítico é duas vezes maior do que o atraso crítico binário. / Since the decade of 60, the improvement of techniques for manufacturing integrated circuits that use binary logic has led to the exponential increase in the density of devices, improving performance, reducing energy consumption and reducing costs of manufacture of integrated circuits in the state of the art. This breakthrough has been achieved historically by the miniaturization of devices, already in nano, starting to reach physical limits to their reduction. In order to give continuity to technological advancement, many studies have proposed the compaction of information through the use of non-binary logic as an alternative for the performance improvement of the state of the art circuits. Accordingly, several studies have been developed in different technologies ranging from bipolar circuits to quantum devices, however, at the moment, no technology demonstrated at the same time the performance requirements, consumption, area and reliability necessary for the application in very large scale of integration. This paper presents a new family of quaternary logic circuits with high performance, low consumption and area, which uses CMOS technology. The circuits developed in this work make use of three power supplies and up to eight different transistors with different threshold voltages, to perform the quaternary logic. Elementary circuits such as inverters and literal circuits are presented and used to implement multiplexers and arithmetic circuits. The circuits are simulated with the SPICE tool using TSMC 0.18 μm technology and the results are compared with equivalent circuits in binary logic. Comparison of a quaternary full adder of four bits, for example, with the equivalent circuit in binary logic shows 55% improvement in speed and 63% in the power consumption for the quaternary implementation and it uses little more than twice the number of transistors. This paper also proposes the use of quaternary logic in FPGA and quaternary configurable logic blocks are developed. Logical mapping results of arithmetic circuits in configurable logic blocks show great reduction in area and power consumption of the quaternary implementation compared to the equivalent binary. In some quaternary circuits, the consumption of power and the number of transistors used are reduced to 3% of consumption and the number of transistors used in the binary equivalent circuits, while the critical delay is two times higher than the binary critical delay.

abstract: Since Duffin and Schaeffer's introduction of frames in 1952, the concept of a frame has received much attention in the mathematical community and has inspired several generalizations. The focus of this thesis is on the concept of an operator-valued frame (OVF) and a more general concept called herein an operator-valued frame associated with a measure space (MS-OVF), which is sometimes called a continuous g-frame. The first of two main topics explored in this thesis is the relationship between MS-OVFs and objects prominent in quantum information theory called positive operator-valued measures (POVMs). It has been observed that every MS-OVF gives rise to a POVM with invertible total variation in a natural way. The first main result of this thesis is a characterization of which POVMs arise in this way, a result obtained by extending certain existing Radon-Nikodym theorems for POVMs. The second main topic investigated in this thesis is the role of the theory of unitary representations of a Lie group G in the construction of OVFs for the L^2-space of a relatively compact subset of G. For G=R, Duffin and Schaeffer have given general conditions that ensure a sequence of (one-dimensional) representations of G, restricted to (-1/2,1/2), forms a frame for L^{2}(-1/2,1/2), and similar conditions exist for G=R^n. The second main result of this thesis expresses conditions related to Duffin and Schaeffer's for two more particular Lie groups: the Euclidean motion group on R^2 and the (2n+1)-dimensional Heisenberg group. This proceeds in two steps. First, for a Lie group admitting a uniform lattice and an appropriate relatively compact subset E of G, the Selberg Trace Formula is used to obtain a Parseval OVF for L^{2}(E) that is expressed in terms of irreducible representations of G. Second, for the two particular Lie groups an appropriate set E is found, and it is shown that for each of these groups, with suitably parametrized unitary duals, the Parseval OVF remains an OVF when perturbations are made to the parameters of the included representations. / Dissertation/Thesis / Doctoral Dissertation Mathematics 2014