Was versteht man unter High-Level Synthese? Wie beschreibt man das Verhalten einer Schaltung in VHDL? Diese zwei Fragen sollen hier erörtert werden. Zuerst wird kurz das High-Level Synthese Programm Caddy vorgestellt und die internen Verarbeitungsschritte kurz aufgezeigt. Dann werden die verschiedenen Stufen der Schaltungsbeschreibbung mit ihren jeweiligen Vor- und Nachteilen diskutiert. Zum Schluss wird noch auf die Grenzen von VHDL-Verhaltensbeschreibungen eingegangen und mögliche Lösungsvorschläge gemacht, um diese Grenzen zu erweitern. Es wird im Grossen und Ganzen nur die momentane Entwicklung zusammengefasst. Dabei soll dieser Bericht auch als Anleitung zur VHDL-Verhaltensbeschreibung dienen.

Für das Erstellen von Schaltungen wird immer mehr die Hardwarebeschreibungssprache VHDL eingesetzt. Sie bietet viele Vorteile gegenüber den bisherigen Beschreibungsmethoden, wie zum Beispiel das Aufbauen der Schaltung mit Hilfe von graphischen CAD Werkzeugen. Ein wichtiger Faktor ist dabei die Entwicklungszeit. Dazu benötigt man aber auch leistungsfähige Syntheseprogramme. Das High-Level Syntheseprogramm Caddy ist nicht in der Lage direkt VHDL-Quelltext zu verarbeiten. Mit dem Programm vh2fg existiert nun die Möglichkeit die VHDL-Beschreibung in ein Flussgraphenformat umzuwandeln, das Caddy verarbeiten kann. Hier wird eine Anleitung gegeben, wie man mit diesem Programm umgeht. Es wird die VHDL-Eingabe spezifiziert und die Ausgabe in Flussgraph erklärt.

With increasing awareness of potential security threats there is a growing interest in communication security for spacecraft control and data. Traditionally commercial and scientific missions have relied on their uniqueness to prevent security breaches. During time the market has changed with open systems for mission control and data distribution, increased connectivity and the use of existing and shared infrastructure. Therefore security layers are being introduced to protect spacecraft communication. In order to mitigate the perceived threats, the Consultative Committee for Space Data Systems (CCSDS) has proposed the addition of communication security in the various layers of the communication model. This thesis describes and discuss their proposal and look into how this application should be implemented into the data link layer of the communication protocol to protect from timing attacks. An implementation of AES-CTR+GMAC is constructed in software to compare different key lengths and another implementation is constructed in synthesized VHDL for use on hardware to investigate the impact on area consumption on the FPGA as well as if it is possible to secure it from cache-timing attacks.

In this thesis, many machine learning algorithms were applied to electrocardiogram (ECG), spectral analysis, and Field Programmable Gate Arrays (FPGAs). In ECG, QRS complexes are useful for measuring the heart rate and for the segmentation of ECG signals. QRS complexes were detected using WaveletCNN Autoencoder filters and ConvLSTM detectors. The WaveletCNN Autoencoders filters the ECG signals using the wavelet filters, while the ConvLSTM detects the spatial temporal patterns of the QRS complexes. For the spectral analysis topic, the detection of chemical compounds using spectral analysis is useful for identifying unknown substances. However, spectral analysis algorithms require vast amounts of data. To solve this problem, B-spline neural networks were developed for the generation of infrared and ultraviolet/visible spectras. This allowed for the generation of large training datasets from a few experimental measurements. Graphical Processing Units (GPUs) are good for training and testing neural networks. However, using multiple GPUs together is hard because PCIe bus is not suited for scattering operations and reduce operations. FPGAs are more flexible as they can be arranged in a mesh or toroid or hypercube configuration on the PCB. These configurations provide higher data throughput and results in faster computations. A general neural network framework was written in VHDL for Xilinx FPGAs. It allows for any neural network to be trained or tested on FPGAs. / Graduate

This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.

Aim of this master's thesis is the creation of serial communication interface for FITkit. This serial interface is a full duplex industrial bus based on 20mA loop circuit and it should allow connection of two FITkits by RS-485. Aim of this paper is to design simple software allowing communication of two FITkits and to secure this communication on RS-485 link against interference or transfer errors.

This thesis deals with the design and implementation of an FPGA-based platform for rapid development of network applications for the COMBO cards family. The proposed platform includes a generic data transfer protocol - FrameLink, a set of tools for FrameLink manipulation, network interface blocks for 1 Gigabit Ethernet, high-speed connection to the software layer via PCI, PCI-X or PCI Express bus and a set of IP cores for network traffic analysis and processing. The benefits of the proposed platform are demonstrated on design and implementation of a network interface card, hardware firewall and exporter of unified packet headers.

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Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal.

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