Made available in DSpace on 2014-12-17T14:55:40Z (GMT). No. of bitstreams: 1 AdautoLT.pdf: 2061017 bytes, checksum: 12a139ba25174e3b22d08cf31c934500 (MD5) Previous issue date: 2009-09-04 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / This work proposes a new methodology to verify those analog circuits, providing an automated tools to help the verifiers to have a more truthful result. This work presents the development of new methodology for analog circuits verification. The main goal is to provide a more automated verification process to certify analog circuits functional behavior. The proposed methodology is based on the golden model technique. A verification environment based on this methodology was built and results of a study case based on the validation of an operational amplifier design are offered as a confirmation of its effectiveness. The results had shown that the verification process was more truthful because of the automation provided by the tool developed / O presente trabalho tem como objetivo desenvolver uma ferramenta de verifica??o para circuitos anal?gicos. O principal objetivo desta ? aumentar a automa??o dos processos de verifica??o. Al?m disso, proporcionar a constru??o de um ambiente de verifica??o capaz de gerar relat?rios ao longo deste processo. Esta metodologia ? baseada na t?cnica do Modelo de Ouro, no entanto, ela tamb?m prop?e uma segunda t?cnica para verificar o modelo de refer?ncia, para se obter resultados mais confi?veis. A metodologia foi utilizada, como estudo de caso, na verifica??o de um amplificador operacional

Made available in DSpace on 2014-12-17T14:55:47Z (GMT). No. of bitstreams: 1 CarlosAAS_DISSERT_1-60.pdf: 4186909 bytes, checksum: cebf9d80edc07d16ef618a3095ead927 (MD5) Previous issue date: 2010-06-30 / This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing / Este estudo consiste na implementa??o e no embarque de uma Rede Neural Artificial (RNA) em hardware, ou seja, em um dispositivo program?vel do tipo field programmable gate array (FPGA). O presente trabalho permitiu a explora??o de diferentes implementa??es, descritas em VHDL, de RNA do tipo perceptrons de m?ltiplas camadas. Por causa do paralelismo inerente ?s RNAs, ocorrem desvantagens nas implementa??es em software, devido ? natureza sequencial das arquiteturas de Von Neumann. Como alternativa a este problema, surge uma implementa??o em hardware que permite explorar todo o paralelismo impl?cito neste modelo. Atualmente, verifica-se um aumento no uso do FPGA como plataforma para implementar as Redes Neurais Artificiais em hardware, explorando o alto poder de processamento, o baixo custo, a facilidade de programa??o e capacidade de reconfigura??o do circuito, permitindo que a rede se adapte a diferentes aplica??es. Diante desse contexto, objetivou-se desenvolver arranjos de redes neurais em hardware, em uma arquitetura flex?vel, nas quais fosse poss?vel acrescentar ou retirar neur?nios e, principalmente, modificar a topologia da rede, de forma a viabilizar uma rede modular em aritm?tica de ponto fixo, em um FPGA. Produziram-se cinco s?nteses de descri??es em VHDL: duas para o neur?nio com uma e duas entradas, e tr?s para diferentes arquiteturas de RNA. As descri??es das arquiteturas utilizadas tornaram-se bastante modulares, possibilitando facilmente aumentar ou diminuir o n?mero de neur?nios. Em decorr?ncia disso, algumas redes neurais completas foram implementadas em FPGA, em aritm?tica de ponto fixo e com alta capacidade de processamento paralelo

Orientador: Marconi Kolm Madrid / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-04T17:12:57Z (GMT). No. of bitstreams: 1 GuardiaFilho_LuizEduardo_M.pdf: 2405031 bytes, checksum: b724836217b8586950a9ffabcd235f35 (MD5) Previous issue date: 2005 / Resumo: Este trabalho de mestrado teve o propósito de projetar e construir um sistema de hard-ware capaz de realizar o controle de máquinas robotizadas em tempo real. Foi dada uma abordagem usando técnicas de processamento paralelo e eletrônica reconfigurável com o uso de dispositivos lógicos programáveis. Mostrou-se em função dos resultados das implementações que o sistema proposto é eficiente para ser utilizado no controle de robôs baseado em modelos matemáticos complexos como cinemático direto/inverso, dinâmico e de visão artificial. Esse mesmo sistema prevê sua utilização para os quatro níveis hierárquicos envolvidos em plantas que se utilizam de controle automático: supervisão, tarefas, trajetória e servomecanismos. O sistema possui interfaces de comunicação USE e RS-232, conversores A/D e D/A, sistema de processamento de imagens (entradas e saídas de sinais de vídeo analógico), portas E/S, chaves e leds para propósito geral. A eficiência foi comprovada através de experimentações práticas utilizando sistemas robóticos reais como: sistema de um pêndulo acionado, robô redundante de 4GDL denominado Cobra, e solução em hardware de funções importantes no sentido da resolução dos modelos matemáticos em tempo real como funções transcendentais / Abstract: This work had as purpose the project and build of a hardware system with abilities to accomplish the real time control of robotic machines. It was given an approach using tech-niques of parallel processing and programmable electronics configuration with programmable logic devices. According to the implementation results, it was shown that this proposed sys-tem is efficient to be used for controlling robots based on complex mathematical models, like direct/inverse kinematics, dynamics and artificial vision. This system foresees its use for the four hierarchical levels involved in industrial plants that use automatic control: supervision, tasks, trajectory /path and servomechanisms. The system has USE and RS-232 communica-tion interfaces, A/D and D/A converters, image processing capabilities (with input/output for analog video signals), I/O ports, and switches and leds for general purpose. Its efficiency is demonstrated through practical experimentations using real robotic systems as: a driven pendu-lum system, a redundant 4 DOF robot called "Cobra", and a hardware solution for important functions in the sense of real time mathematical models computing, like the transcendental functions / Mestrado / Automação / Mestre em Engenharia Elétrica

Le développement des systèmes multiprocesseurs intégrés sur puce (MPSoC) répond au besoin grandissant des architectures de calcul intensif. En revanche, l'évolution de leurs performances est entravée par leurs réseaux de communication sur puce (NoC) à cause de leur consommation d'énergie ainsi que du retard. C'est dans ce contexte que les NoC à base d'interconnexions RF et filaires (RFNoC) ont émergé. Afin de gérer au mieux et d'optimiser la conception d'un RFNoC, il est indispensable de développer une plateforme de simulation intégrant à la fois des circuits analogiques et numériques.Dans un premier temps, la simulation temporelle d'un RFNoC avec des composants dont les modèles sont idéaux est utilisée pour optimiser l'allocation des ressources spectrales disponibles. Le cas échéant, nous proposons des solutions pour améliorer la qualité de signal transmis. Dans un deuxième temps, nous avons développé en VHDL-AMS des modèles comportementaux et précis de chacun des composants du RFNoC. Les modèles de l'amplificateur faible bruit (LNA) et du mélangeur, prennent en compte les paramètres concernant, l'amplification, les non-linéarités, le bruit et la bande passante. Le modèle de l'oscillateur local considère les paramètresconventionnels, notamment le bruit de phase. Quant à la ligne de transmission, un modèle fréquentiel précis, incluant l'effet de peau est adapté pour les simulations temporelles. Ensuite, l'impact des paramètres des composants sur les performances du RFNoC est évalué afin d'anticiper les contraintes qui s'imposeront lors de la conception du RFNoC. / The development of multiprocessor systems integrated on chip (MPSoC) respondsto the growing need for intensive computation systems. However, the evolutionof their performances is hampered by their communication networks on chip(NoC) due to their energy consumption and delay. It is in this context that the wired RF network on chip (RFNoC) was emerged. In order to better manage and optimize the design of an RFNoC, it is necessary to develop a simulation platform adressing both analog and digital circuits.First, a time domaine simulation of an RFNoC with components whose modelsare ideal is used to optimize the allocation of the available spectrum resources. Where appropriate, we provide solutions to improve the quality of transmitted signal. Secondly, we have developed, in VHDL-AMS, behavioral and accurate models of all RFNoC components. The models of the low noise amplifier (LNA) and the mixer take into account the parameters for the amplification, nonlinearities, noise and bandwidth. The model of the local oscillator considers the conventional parameters, including its phase noise. Concerning the transmission line, an accurate frequency model, including the skin effect is adapted for time domaine simulations. Then, the impact of component parameters on RFNoC performances is evaluatedto anticipate constraints of the RFNoC design.

V systému s kódy zbytkových tříd je základem skupina navzájem nezávislých bází. Číslo ve formátu integer je reprezentováno kratšími čísly integer, které získáme jako zbytky všech bází, a aritmetické operace probíhají samostatně na každé bázi. Při aritmetických operacích nedochází k přenosu do vyšších řádů při sčítání, odečítání a násobení, které obvykle potřebují více strojového času. Srovnávání, dělení a operace se zlomky jsou komplikované a chybí efektivní algoritmy. Kódy zbytkových tříd se proto nepoužívají k numerickým výpočtům, ale jsou velmi užitečné pro digitální zpracování signálu. Disertační práce se týká návrhu, simulace a mikropočítačové implementace funkčních bloků pro digitální zpracování signálu. Funkční bloky, které byly studovány jsou nově navržené konvertory z binarní do reziduální reprezentace a naopak, reziduální sčítačka a násobička. Nově byly také navržené obslužné algoritmy.

This thesis deals with the communication on the PCI bus and the design of controllers for the PCI card with FPGA circuit. The introduction shows the functionality and structure of FPGA circuits, followed by description of the principle of communication through the PCI bus. After an analysis of the PCI the thesis describes a design of controllers for a target card and lets the reader get acquainted with its different parts. In the process of implementation carefully examines the structure and operation of individual blocks of PCI controller. In the following part the thesis shows the process of implementation and testing of the final solution using the educational card with FPGA circuit.

The Master's thesis Transformation of the microprocessor's description language to the hardware description language is aimed at design of application specific microprocessors with using ISAC language. It deals with design and implementation of transformation which converts description of microprocessor in ISAC language into equivalent description in VHDL language. The chapter Summary of research problems describes chosen problems, showing up some notions connected with problems and presents suggestion of transformation mentioned above. The chapter Suggestion of solution presents new extension of ISAC language. There is also described the way of design solution of transformation and solution of implementation of VHDL generator which performs transformation. Conclusion of thesis discusses next points of future work reached results.

Several technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification, GPS, Wi-Fi among others. Current technologies utilizing microprocessors increase the device's power consumption. In this project, a Verilog Hardware Language (VHDL) designed handheld device that autonomously guides a visually impaired user through an obstacle free path is proposed. The goal is to minimize power consumption by not using the usual microcontroller and replacing it with components that can increase its speed. Utilizing six infrared sensors, the handheld device is modeled after current technologies which use IR and sonar sensors which are reviewed in this project. By using behavioral modeling, an algorithm for obstacle avoidance and the generation of the obstacle free path is reduced using a K-map and implemented using a multiplexer. / by Ernesto Cividanes. / Thesis (M.S.C.S.)--Florida Atlantic University, 2010. / Includes bibliography. / Electronic reproduction. Boca Raton, Fla., 2010. Mode of access: World Wide Web.

Made available in DSpace on 2015-04-14T13:56:23Z (GMT). No. of bitstreams: 1 438862.pdf: 6841213 bytes, checksum: 62ab6904af18caf353f011769efc8178 (MD5) Previous issue date: 2012-03-30 / This work proposes a new time and frequency synchronization system for OFDM (Orthogonal Frequency Division Multiplexing) receivers. Presently, the OFDM technique is adopted in nearly all wireless broadband systems (IEEE 802.16 WiMax, 3GPP-LTE, IEEE 802.22, etc). It is also used in the ISDB-T digital television system, adopted in Brazil. The proposed synchronization system controls the receiver timing and frequency in a closed loop, adjusting the FFT window delay and the local oscillator frequency. The loop error is measured in the frequency domain, based on reference symbols inserted on pilot carriers in the transmitter. Initialization of the closed loop operating point is performed with base on the guard interval generated at the transmitter. Di erently of the usual sync implementations for OFDM systems, the proposed system actuates in the time domain, instead of the frequency domain. Also, in order to avoid loop instabilities due to the transport delay intrinsic to the OFDM demodulation process, the proposed system uses a prediction algorithm for loop stabilization. / Este trabalho prop?e uma nova implementa??o do sistema de sincronismo de tempo e frequ?ncia para receptores OFDM (Orthogonal Frequency Division Multiplexing). A t?cnica OFDM e utilizada no sistema de TV digital adotado no Brasil (ISDB-T), bem como na quase totalidade das tecnologias para wireless broadband atualmente no mercado (IEEE 802.16 WiMax, 3GPP-LTE, IEEE 802.22, etc). O sistema de sincronismo aqui proposto controla frequ?ncia e timing do receptor em malha fechada, atuando no atraso ou no adiantamento dos dados na entrada da FFT e na frequ?ncia do oscilador local. A medi??o do erro da malha e efetuada no dom?nio frequ?ncia, tendo como refer?ncia s?mbolos pilotos inseridos em frequ?ncia no sinal transmitido. A inicializa??o do ponto de opera??o da malha fechada e baseado no intervalo de guarda inserido no sinal pelo transmissor. Ao contrario das implementa??es usuais para sincronismo em sistemas OFDM, a atua??o do sistema e no dom?nio tempo, e n?o no dom?nio frequ?ncia. Ainda, para evitar instabilidade da malha dado o atraso de transporte intr?nseco na demodulac?o de um sinal OFDM, esta ? estabilizada atrav?s de algoritmo de predi??o.

Em todo desenvolvimento, seja ele eletrônico ou não, existe sempre a necessidade de realização de testes, com o objetivo de avaliar, validar e aperfeiçoar o sistema projetado. Os sistemas de telemetria permitem observar as mais diversas fontes de dados à distância, onde o acompanhamento de determinadas características de um equipamento possa ser realizado diretamente no ambiente onde ele será utilizado. Apesar de ser grande a aplicação dos sistemas de telemetria, o custo de equipamentos utilizados para este fim é normalmente muito elevado. Este trabalho apresenta uma solução que atende aplicações específicas de sistemas de telemetria visando um baixo custo de implementação. Como exemplo, é apresentado o caso de um sistema desenvolvido para a indústria de defesa.