published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

Η παρούσα διπλωματική εργασία πραγματοποιήθηκε από 8/2013-9/2014 στο τμήμα ηλεκτρολόγων μηχανικών & τεχνολογίας υπολογιστών του πανεπιστημίου Πατρών, υπό την επίβλεψη του καθηγητή Γαβριήλ Γιαννακόπουλου. Σκοπός της παρούσας διπλωματικής είναι η σχεδίαση και ο έλεγχος στατικού σειριακού αντισταθμιστή με στόχο την αντιστάθμιση συμμετρικών και ασύμμετρων βυθίσεων τάσης σε ευαίσθητα φορτία. Αρχικά γίνεται μια γενική αναφορά στην δομή των συστημάτων ηλεκτρικής ενέργειας στην έννοια της ποιότητας ισχύος και στις διαταραχές που μπορούν να εμφανιστούν σε ένα σύστημα ηλεκτρικής ενέργειας. Έπειτα παρουσιάζονται μέθοδοι βελτίωσης της ποιότητας ισχύος και συγκεκριμένα των διαταραχών που οφείλονται σε βυθίσεις τάσεις. Κατόπιν περιγράφεται η δομή και ο τρόπος λειτουργίας της διάταξης που θα χρησιμοποιηθεί για την αντιστάθμιση της τάσης (Στατικός Σειριακός Αντισταθμιστής). Αναλύεται το σύστημα ελέγχου (Διπλός Διανυσματικός Ελεγκτής, Double Vector Controller) και παρουσιάζονται τα αποτελέσματα της προσομοίωσης διαφόρων τύπων βραχυκυκλωμάτων με την χρήση του Στατικού Σειριακού Αντισταθμιστή (Static Series Compensator). / The present work was carried out by 8 / 2013-9 / 2014 in the Department of Electrical and Computer Engineering,in the University of Patras, under the supervision of Professor Gabriel Giannakopoulos. The purpose of this project is the design and control of serial static compensator designed to compensate symmetrical and asymmetrical voltage drops to sensitive loads. Originally made ​​a general reference to the structure of power systems in the sense of power quality and disturbances that can occur in a power system. Then, the study methods for improving power quality and specific disorders caused dips trends. After describing the structure and function of the device to be used to compensate for the voltage (Serial Static Compensator). Analyzed control system, Double Vector Controller and presented the results of the simulation of various types of short circuits using the Serial Static Compensator

The primary goal of this work was to examine the role of voltage-dependent Ca2+ channels in regulating the output of larval Drosophila motoneurons functioning within an intact network. To accomplish this goal, two major aims were addressed: 1. To determine whether larval Drosophila motoneurons express voltage-dependent Ca2+ channels in their central processes, and further, to determine the genes responsible. 2. To determine the role of centrally expressed voltage-dependent Ca2+ channels in the regulation of motoneuron output as motoneurons receive behaviorally relevant input from the locomotor network. To address these goals, genetic tools available in Drosophila were used along side in situ patch clamp techniques from larval motoneurons.Using whole cell voltage-clamp techniques in situ, we have shown that two identified motoneurons, aCC and RP-2, carry voltage-dependent currents recorded from the soma. Dmca1D, the L-type like channel in Drosophila, is primarily responsible for this current. Expressing Dmca1D RNAi in aCC and RP-2, as the preparation displayed fictive bouts of locomotion, caused an increase in burst duration in both RP-2 and aCC as well as an increase in the number of action potentials fired per burst. Additionally, the afterhyperpolarization between spikes was greatly reduced and spiking became less regular. This work indicates a role for Dmca1D in the processing of synaptic information in Drosophila motoneurons aCC and RP-2.

SAR-ADCs are very popular and suitable for conversions up to few tens of MHz with 8 to 12 bits of resolution. A very popular type is the Charge Redistribution SAR-ADC which is based on a capacitive array. Higher speeds can be achieved by using the interleaving technique where a number of SAR-ADCs are working in parallel. These speeds, however, can only be achieved if the reference voltage can cope with the switching of the capacitive array. In this thesis the design of a programmable voltage reference generator for a Charge Redistribution SAR-ADC was studied. A number of architectures were studied and one based on a Current Steering DAC was chosen because of the settling time that could offer to the Charge Redistribution SAR-ADC switching operation. This architecture was further investigated in order to spot the weak points of the design and try to minimize the settling time. In the end, the final design was evaluated and possible trimming techniques were proposed that could further speed up the design.

This thesis presents the design and implementation of PMOS-based integrated charge pumps with extended voltage range and their regulation circuits in a standard process. The performance of charge pumps are evaluated by their output resistances and power conversion efficiencies. Formulas which describe the charge pump characteristics are developed and presented. Existing charge pumps are analyzed and studied to understand their limitations in generating high voltages and achieving high performance. The proposed charge pump structures are designed to use PMOS switches to alleviate the high voltage stresses across transistors by biasing their bulk independently. The voltages across transistors and capacitors are kept within the suggested voltage rating (VDD)regardless of how high the output voltage is, thus the maximum voltage range is extended and no longer limited by the breakdown voltages of the devices. The charge pump circuits only need low-voltage devices and standard processes, and can be easily integrated in a digital or mixed-signal design. The proposed charge pump regulation circuits include a voltage divider, a voltage controlled ring oscillator and a feedback operational amplifier. The regulation circuits are able to adjust the clock frequency to regulate the charge pump to a steady output voltage (set by the reference voltage) under a large range of current loads. A test chip including the proposed charge pumps and regulation circuits was fabricated in a 0.18 um digital CMOS process provided by Taiwan Semiconductor Manufacturing Company (TSMC). The proposed charge pumps were tested and demonstrated the reliable generation of output voltages up to 11.47 V using only low-voltage devices. The simulation and measurement results have been presented and compared, demonstrating the functionality and performance of the proposed circuits. / Kapik Integration, Mitacs

This thesis deals with the problem of control system design for power electronic controllers when high performance is desired despite unaccounted for internal and external conditions. Factors such as parameter variations, operating condition changes, and filtering and measurements delays, may adversely impact the performance of a circuit whose controller design is not immune to external and internal disturbances. The thesis explores the method of internal model design as a viable approach for designing controllers with superior performance despite system variations. Following a presentation of the theoretical background of the internal model design, the thesis considers two examples of state variable models, improving the stability of a voltage source converter and speed control of an induction motor. Conclusions show the new control system is more stable and offers better controllability despite unexpected system variations, compared to classical control system.

The development of a DC-DC converter for use in a proposed range of one to ten kilowatt off-line power supplies is presented. The converter makes good use of established design practices and recent technical advances. The thesis begins with a review of traditional design practices, which are used in the design of a 3kW, 48V output DC-DC converter, as a bench-mark for evaluation of recent technical advances. Advances evaluated include new converter circuits, control techniques, components, and magnetic component designs. Converter circuits using zero voltage switching (ZVS) transitions offer significant advantages for this application. Of the published converters which have ZVS transitions the phase shift controlled full bridge converter is the most suitable, and assessments of variations on this circuit are presented. During the course of the research it was realised that the ZVS range of one leg of the phase shift controlled full bridge converter could be extended by altering the switching pattern, and this new switching pattern is proposed. A detailed analysis of phase shift controlled full bridge converter operation uncovers a number of operational findings which give a better and more complete understanding of converter operation than hitherto published. Converter design equations and guidelines are presented and the effects of the new improvement are investigated by an approximate analysis. Computer simulations using PSPICE2 are carried out to predict converter performance. A prototype converter design, construction details and test results are given. The results obtained compare well to the predicted performance and confirm the advantages of the new switching pattern.

Although Voltage Varying (VV) strategies like Conservation Voltage Reduction (CVR) are widely used by utilities to reduce the overall energy consumption and peak power demand of distribution feeders, it is aberrant among industrial customers. This research proposes a Voltage Varying (VV) strategy for industrial customers that takes into account their complex characteristics and unique set of constraints. Unlike VV strategies for Local Distribution Companies (LDC), those for an industrial customers are far more complex, and require specific c load modelling and process estimation to infer the optimal operating voltage for the industrial load. The proposed VV technique referred to as Voltage Optimization (VO), is a generic and comprehensive framework that seeks to reduce the energy consumption of the industrial load vis-~a-vis the bus voltage. It utilizes a Neural Network (NN) model of the industrial load, trained using historical operating data, to estimate the real power consumption of the load, based on the bus voltage and overall plant process. This load model, is incorporated into the proposed VO model, whose objective is the minimization of the energy drawn from the substation and the switching operations of Load Tap Changers (LTC). The proposed VO framework is tested on load models developed using simulated and real data. Results suggest that the proposed technique can be successfully implemented by industrial customers or plant operators to improve their energy savings, in comparison to existing VV techniques.

Thesis (M.S.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references (ℓ. 49)

Thesis (Ph. D.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 93-97). Also available on the World Wide Web.