.... Das Wissen über die Baustoffe allein reicht nicht aus, um sichere Bauwerke zu errichten. Auch das Wissen über das Verhalten von Baustrukturen unter Einwirkungen ist dafür notwendig. Der Lehrstuhl für Statik, der sich hauptsächlich dieser Thematik widmet, darf mit Recht als Vorreiter an der Fakultät Bauingenieurwesen bei der Untersuchung von Sicherheitsfragen für Bauwerke gelten.... (aus dem Vorwort)

In the first part of this thesis we generalise the well-known K-terminal reliability R(G,K) to different kinds of terminal vertices. By means of lattice theoretic tools, we propose a divide and conquer approach to compute this new reliability measure efficiently. The first part concludes with an improved path decomposition algorithm that computes R(G,K) much more memory and time efficient compared to current state-of-the-art algorithms. In the second part we discuss the counting of connected set partitions of a graph G and its application to network reliability problems. Again we utilise the lattice theoretic approach to carry out the counting efficiently. Finally, we investigate the domination reliability DR(G) of a graph G as an interesting network reliability measure.

Subjects in laboratory experiments are prone to effects of social desirability. This reactive behavior is due to the subjects perceived anonymity in the entire experiment. Especially, socially desirable behavior is also triggered by assembling and/or payment procedures that are not anonymous. Indeed, in a laboratory experiments with a one-shot prisoner’s dilemma (PD) and perfect stranger anonymity subjects (n=174) showed significantly different cooperation rates depending on the anonymity conditions during assembling and the payment procedure, ranging from 33.3% to 19.9%. In addition, a first experiment with the PD and anonymous payment and double blind experimenting lead to a cooperation rate of 33.3%. Only after the same subjects (n=34) took part a second time in same, entire experiment, the cooperation rate fell to 8.8%. Therefore this measurement of the cooperation rates in a laboratory experiment failed the test-retest check on reliability. This happened though all manipulations used fulfilled the standards of fully anonymous experimenting. This means that such processes could go unnoticed and bias the results of any standard laboratory experiment on cooperation in one shot decisions. Therefore, in accordance with the textbook logic of laboratory experiments, but in contrast to a common practice (cf. Behavioral Game Theory) marginal totals from cooperation experiments in the laboratory should not be interpreted.

The realization of wireless ultra-reliable low-latency communications (URLLC) is one of the key challenges of the fifth generation (5G) of mobile communications systems and beyond. Ensuring ultra-high reliability together with a latency in the (sub-)millisecond range is expected to enable self-driving cars, wireless factory automation, and the Tactile Internet. In wireless communications, reliability is usually only considered as percentage of successful packet delivery, aiming for 1 − 10⁻⁵ up to 1 − 10⁻⁹ in URLLC.

Die Chemnitzer Linux-Tage sind eine Veranstaltung rund um das Thema Open Source. Im Jahr 2013 wurden 106 Vorträge und Workshops gehalten. Der Band enthält ausführliche Beiträge zu 11 Hauptvorträgen sowie Zusammenfassungen zu 95 weiteren Vorträgen.

In the first part of this thesis we generalise the well-known K-terminal reliability R(G,K) to different kinds of terminal vertices. By means of lattice theoretic tools, we propose a divide and conquer approach to compute this new reliability measure efficiently. The first part concludes with an improved path decomposition algorithm that computes R(G,K) much more memory and time efficient compared to current state-of-the-art algorithms. In the second part we discuss the counting of connected set partitions of a graph G and its application to network reliability problems. Again we utilise the lattice theoretic approach to carry out the counting efficiently. Finally, we investigate the domination reliability DR(G) of a graph G as an interesting network reliability measure.

.... Das Wissen über die Baustoffe allein reicht nicht aus, um sichere Bauwerke zu errichten. Auch das Wissen über das Verhalten von Baustrukturen unter Einwirkungen ist dafür notwendig. Der Lehrstuhl für Statik, der sich hauptsächlich dieser Thematik widmet, darf mit Recht als Vorreiter an der Fakultät Bauingenieurwesen bei der Untersuchung von Sicherheitsfragen für Bauwerke gelten.... (aus dem Vorwort)

We have already known for a long time that hardware components are not perfect and soft errors in terms of single bit flips happen all the time. Up to now, these single bit flips are mainly addressed in hardware using general-purpose protection techniques. However, recent studies have shown that all future hardware components become less and less reliable in total and multi-bit flips are occurring regularly rather than exceptionally. Additionally, hardware aging effects will lead to error models that change during run-time. Scaling hardware-based protection techniques to cover changing multi-bit flips is possible, but this introduces large performance, chip area, and power overheads, which will become non-affordable in the future. To tackle that, an emerging research direction is employing protection techniques in higher software layers like compilers or applications. The available knowledge at these layers can be efficiently used to specialize and adapt protection techniques. Thus, we propose a novel adaptable and on-the-fly hardware error detection approach called AHEAD for database systems in this paper. AHEAD provides configurable error detection in an end-to-end fashion and reduces the overhead (storage and computation) compared to other techniques at this level. Our approach uses an arithmetic error coding technique which allows query processing to completely work on hardened data on the one hand. On the other hand, this enables on-the-fly detection during query processing of (i) errors that modify data stored in memory or transferred on an interconnect and (ii) errors induced during computations. Our exhaustive evaluation clearly shows the benefits of our AHEAD approach.

Leistungshalbleiter werden in Windenergieanlagen, Elektroautomobilen und vielen anderen Applikationen eingesetzt, bei denen die elektrische Energie in eine spezielle Form zu wandeln ist, um etwa Netzeinspeisung bei Windenergieanlagen oder eine spezifische Beschleunigung bei Elektroautomobilen zu realisieren. Bei ihrem Einsatz altern sie, dabei spielen Lastwechsel eine besondere Rolle. Es wird untersucht, welche Aspekte eine wichtige Rolle bei der Lastwechselbelastung einnehmen, wie sie zu berechnen und zu berücksichtigen sind. Am Beispiel von Leistungsmessdaten zweier an der mittelnorwegischen Küste betriebenen Windenergieanlagen wird beispielhaft gezeigt, wie die Lastwechselbelastung ermittelt werden kann. Im Rahmen der Arbeit wurde ein modularer 2000A Lastwechseltester entwickelt, gebaut und in Betrieb genommen, der mit einer neuen VCE(T) Kalibriermethode, der Aktiven Kalibrierung, ausgerüstet ist. Tester und Kalibriervorgang werden vorgestellt und im Detail diskutiert. Auf dieser Basis werden Perspektiven aufgezeigt, wie Lastwechseltester zukünftig optimiert gestaltet und die Messmethoden zur Alterungsbestimmung in die Applikation überführt werden können. / Power semiconductors are deployed in wind mills, electrical cars and many other applications whenever electrical energy has to be transformed into an intended form e.g. to feed-in wind energy or to accelerate a car. In use they fatigue at which power cycles play an important role. This work investigates the aspects taking the main role at power-cycle load, how they are to calculate and how to be considered. Based on power measurements of two wind mills placed at the middle Norwegian coast, it is shown how to determine the power cycle load. A modular 2000A power cycling test equipment has been developed, built-up and run-in. By means of this equipment a new VCE(T) calibration-method is demonstrated. The equipment as well as the calibration procedure is presented and discussed in detail. On that basis perspectives are depicted how power cycle equipment can be optimized and, moreover, methods for fatigue determination can be transferred from laboratory into application.

The key objective of database systems is to reliably manage data, whereby high query throughput and low query latency are core requirements. To satisfy these requirements, database systems constantly adapt to novel hardware features. Although it has been intensively studied and commonly accepted that hardware error rates in terms of bit flips increase dramatically with the decrease of the underlying chip structures, most database system research activities neglected this fact, leaving error (bit flip) detection as well as correction to the underlying hardware. Especially for main memory, silent data corruption (SDC) as a result of transient bit flips leading to faulty data is mainly detected and corrected at the DRAM and memory-controller layer. However, since future hardware becomes less reliable and error detection as well as correction by hardware becomes more expensive, this free ride will come to an end in the near future. To further provide a reliable data management, an emerging research direction is employing specific and tailored protection techniques at the database system level. Following that, we are currently developing and implementing an adopted system design for state-of-the-art in-memory column stores. In our lightning talk, we will summarize our current state and outline future work.