Smarte Prüfsysteme werden ein Schlüsselbaustein zur Qualitätssicherung in der industriellen Fertigung und Produktion sein. Insbesondere trifft dies auf komplexe Prüf- und Bewertungsprozesse zu. In den letzten Jahren haben sich hierfür lernbasierte Verfahren als besonders vielversprechend herauskristallisiert. Ihr Einsatz geht in der Regel mit erheblichen Performanceverbesserungen gegenüber konventionellen, regel- bzw. geometriebasierten Methoden einher. Der Black-Box-Charakter dieser Algorithmen führt jedoch dazu, dass die Interpretationen der berechneten Prognosegüten kritisch zu hinterfragen sind. Das Vertrauen in die Ergebnisse von Algorithmen, die auf maschinellem Lernen basieren, kann erhöht werden, wenn verschiedene, voneinander unabhängige Verfahren zum Einsatz kommen. Hierbei sind Datenfusionsstrategien anzuwenden, um die Resultate der verschiedenen Methoden zu einem Endergebnis zusammenzufassen. Im Konferenzbeitrag werden, aufbauend auf einer kurzen Vorstellung wichtiger Ansätze zur Objektklassifikation, entsprechende Fusionsstrategien präsentiert und an einem Fallbeispiel evaluiert. Im Anschluss wird auf Basis der Ergebnisse das Potential der Datenfusion in Bezug auf das Maschinelle Lernen erörtert.

Die Untersuchung von Zuverlässigkeitsnetzwerken geht bis zum frühen 20. Jahrhundert zurück. Diese Arbeit beschäftigt sich hauptsächlich mit der Zweifach-Kantenzusammenhangswahrscheinlichkeit. Zuerst werden einfache Algorithmen, die aber für allgemeine Graphen nicht effizient sind, gezeigt, zusammen mit Reduktionen. Weiterhin werden Charakterisierungen von Kanten bezogen auf Wegemengen gezeigt. Neue strukturelle Bedingungen für diese werden vorgestellt. Neue Ergebnisse liegen ebenfalls für Graphen hoher Dichte und Symmetrie vor, genauer für vollständige und vollständig bipartite Graphen. Naturgemäß sind Graphen von geringer Dichte hier einfacher in der Untersuchung. Die Arbeit zeigt Ergebnisse für Kreise, Räder und Leiterstrukturen. Graphen mit beschränkter Weg- beziehungsweise Baumweite haben polynomiale Algorithmen und in Spezialfällen einfache Formeln, die ebenfalls vorgestellt werden. Der abschließende Teil beschäftigt sich mit Schranken und Approximationen.

With the advent of Internet of Things (IoT), an increasing number of devices start exchanging information. This puts emphasis on wireless sensor networks (WSNs) to facilitate the interaction with the environment in varied application scenarios such as, for example, building and home automation among others. In this context, a reliable communication is usually required, i.e., it is necessary to guarantee that packets arrive within a specified maximum delay or deadline. In addition, since nodes are usually battery-powered and deployed in large numbers, they must be cost-effective and economize on energy, which requires nodes to have a low complexity. In this context, unidirectional communication, i.e., where nodes either send or receive data, seems to be an interesting solution. Since no elaborate feedback mechanisms such as carrier sensing, acknowledgments and retransmissions schemes are possible, complexity, costs, energy consumption and communication overhead are reduced in a considerable manner. On the other hand, however, packet loss becomes more likely making such networks strongly unreliable. To overcome this predicament, two MAC (Medium Access Control) protocols are proposed, namely DEEP and RARE. These consist in nodes transmitting their data as sequences of redundant packets with carefully selected inter-packet separations leading to robust transmission patterns that enable reliable communication. In the case of DEEP, full (100%) reliability can be guaranteed, i.e., there is no data loss, which is particularly useful for safety critical applications. RARE, on the other hand, is designed for applications that tolerate some amount of data loss and can be configured to a reliability <100%, i.e., to a certain probability on successful data delivery. This allows improving other aspects of the network, such as energy consumption, communication delays, etc. In contrast to solutions from the literature, the proposed protocols do not pursue a best-effort approach, but rather provide an analytical framework to assess the performance (i.e., reliability, energy consumption, etc.) of the network. In addition, the proposed protocols are based on more general models that allow describing arbitrary node types with different deadlines and packet lengths leading to a provable higher performance. These and other benefits are illustrated by the means of extensive numerical experiments and simulations based on the OMNeT++ framework.

The growing interest in high speed and RF technologies assert for the importance of reliability characterization beyond the conventional DC methodology. In this work, the influence of bias temperature instability (BTI) stress on RF small signal parameters is shown. The correlation between degradation of DC and RF parameters is established which enables the empirical modelling of stress induced changes. Furthermore, S-Parameters characterization is demonstrated as the tool to qualitatively distinguish between HCI and BTI degradation mechanisms with the help of extracted small signal gate capacitances.

This paper describes the failure detection system of an electro-hydraulic actuator with dual modular redundancy based on a hybrid twin TM concept. Hybrid twin TM is a combination of virtual twin that operates in parallel with the actuator and represents its ideal behaviour, and a digital twin that identifies possible failures using the sensor readings residuals. Simulation-based system reliability analysis helps to generate a dataset for training the digital twin using machine learning algorithms. A systematic failure detection approach based on decision trees and the process of analysing the quality of the result is described.

Model-based design is a common methodology in the development of embedded complex control systems. Control system engineers typically prefer to use MATLAB® Simulink® and suitable automatic code generators for the development and deployment of software. Embedded systems are subject to random hardware faults; bit-flips, for example, may affect random access memory (RAM) cells and central processing unit (CPU) registers and cause data errors that may propagate to critical system outputs and result in system failures. From a dependability perspective, the design space of control systems includes the selection of a suitable (reliable) implementation of a control algorithm. Such algorithm can be implemented with model-based software development frameworks, such as Simulink using different, but functionally equivalent implementations. However, these functional equivalents may exhibit completely different reliability properties. This thesis proposes an analytical method for the evaluation of the reliability properties of control systems that are designed with Simulink models. The method is based on a transformation of the assembly code, which is generated from the Simulink model, into a formal stochastic error propagation model as well as its quantification through underlying Markov chain models and state-of-the-art probabilistic model-checking techniques. The application of the method to the functionally equivalent implementations can determine which one is less vulnerable to data errors due to random hardware faults. Fault tolerance is significant to dependable system design. Control systems can be protected with fault tolerance mechanisms to increase the reliability. Redundancy is the key underlying concept for achieving fault tolerance that is usually implemented at the hardware or software level. In the case of model-based development, redundancy mechanisms are preferable for direct application at the model level (Simulink model level). This thesis introduces a systematic classification of fault-tolerant design patterns. Such patterns can be applied to the Simulink model to tolerate random hardware faults, and taken into account during the control system design. In addition, it is more transparent and convenient for control system engineers to directly protect vulnerable parts with fault tolerance mechanisms at the model level. The rigorous reliability assessment of the embedded control systems must be conducted at the assembly level based on the modeling of data errors that occurred in RAM and CPU. However, the scalability of the assembly-level assessment method is challenging and even problematic in view of the state space explosion (SSE) problem of the underlying Markov chain models. The computational complexity may increase exponentially as the assembly code size increases. Moreover, the transformation from the Simulink models to the assembly code is a complicated procedure. It is also more convenient for control engineers to already be able to estimate reliability properties and implement possible reliability improvements at the model level in the early design phase, when the model-based design is actually applied. Therefore, this thesis proposes a model-level reliability evaluation of Simulink models to address the aforementioned problems. The efficiency of the proposed modellevel evaluation is verified by a comparison of the reliability properties that are assessed at the assembly and model levels.:1. Introduction 2. Preliminaries 3. Reliability evaluation of control algorithm implementations at the assembly level 4. Fault-tolerant design patterns 5. MORE: MOdel-based REdundancy for Simulink models 6. Model-level assessment of Simulink models 7. Conclusion

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

The hardware as well as software communities have recently experienced a shift towards mitigating bit flips issues in software, rather than completely mitigating only in hardware. For this software error mitigation, arithmetic error coding schemes like AN coding are increasingly applied because arithmetic operations can be directly executed without decoding and bit flip detection is provided in an end-to-end fashion. In this case, each encoded data word is computed by multiplying the original data word with a constant integer value A. To reliably detect b bit flips in each code word, the value A has to be well-chosen, so that a minimum Hamming distance of b + 1 can be guaranteed. However, the value A depends on the data word length as well as on the desired minimum Hamming distance. Up to now, a very expensive brute force approach for computation of the value for A is applied. To tackle that in a more efficient way, we present a lower bound-oriented approach for this calculation in this paper.

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257 / Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257

With the discovery of the ferroelectric (FE) properties within HfO₂, the scaling gap between state-of-the-art technology nodes and non-volatile memories based on FE materials can be bridged. In addition to non-volatility, new memory concepts should guarantee sufficient endurance and operation stability. However, in contrast to optimized perovskite based FEs, binary oxide based FE memories still show changes in the memory window (MW) followed by either hard breakdown or closure of the MW. Recently, we have shown that anti-FE (AFE) materials exhibit very stable and significantly higher endurance with respect to the FE counterparts. Inspired by the robustness and remarkable cycling performance of the AFE materials, we analyze the remaining reliability aspects of these devices. By characterizing the pure film properties of capacitor stacks and switching performance when integrated into devices, we compare and investigate temperature stability, imprint, retention, and variability of both FE and AFE memories. We investigate if the lower energetic barrier to be overcome together with partial switching and lower switching induced stress are responsible for the higher endurance of the AFE with respect to the FE based memories. By utilizing charge trapping and charge pumping tests together with leakage current spectroscopy in combination with comprehensive modeling we check that assumption. Moreover, we identify the interfacial buffer layer as the weakest link of these devices.