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A logic built-in self-test architecture that reuses manufacturing compressed scan test patternsJosé Costa Alves, Diogo 31 January 2009 (has links)
Made available in DSpace on 2014-06-12T15:52:41Z (GMT). No. of bitstreams: 1
license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5)
Previous issue date: 2009 / A busca por novas funcionalidades no que diz respeito a melhoria da
confiabilidade dos sistemas eletrônicos e também a necessidade de gerir
o tempo gasto durante o teste faz do mecanismo Built-in-Self-Test (BIST)
um característica promissora a ser integrada no fluxo atual de
desenvolvimento de Circuitos Integrados (IC). Existem vários tipos de
BIST: Memories BIST, Logical BIST (LBIST) e também alguns
mecanismos usados para teste as partes analógicas do circuito. O LBIST
tradicional usa um hardware on-chip para gerar todos os padrões de teste
com um gerador pseudo aleatório (PRPG) e analisa a assinatura de saída
gerada por um registrador de assinatura de múltipla entradas (MISR).
Essa abordagem requer a inserção de pontos de teste extras or
armazenagem de informação fora do chip que tornará possível alcançar
uma cobertura de teste > 98%. Também a geração de todos os estímulos
de teste implica no sacrifício no tempo aplicação do teste, o qual pode ser
aceitável para pequenos sistemas executarem auto-teste durante a
inicialização do sistema mas pode tornasse um aspecto negativo quando
testando System-on-chip (SOC) ICs. O fluxo corrente de desenvolvimento
de um IC insere scan chains e gera automaticamente padrões de teste de
scan para alcançar uma alta cobertura para o teste de manufatura.
Técnicas de compressão de dados provaram ser muito úteis para reduzir
o custo de teste enquanto reduzem o volume de dados e o tempo de
aplicação dos testes. Esse trabalho propõe o reuso de padrões de teste
comprimidos usados durante o teste de manufatura para implementar um
LBIST com objetivo de testar o circuito quando ele já está em campo. O
mecanismo LBIST proposto objetiva descobrir defeitos que podem ocorrer
devido ao desgasto do circuito. Uma arquitetura e um fluxo de
desenvolvimento semi-automático do mecanísmo LBIST baseado em
padrões de teste de scan são propostos e validados usando um SoC real
como caso de teste
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Poznámky k problematice tzv. knowledge classHamplová, Dana, January 1998 (has links)
No description available.
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A chemical programming language for orchestrating services : Application to interoperability problems / Un langage de programmation chimique pour l’orchestration des services : Application aux problèmes d’interopérabilitéLacouture, Mayleen 31 October 2014 (has links)
Avec l’émergence du "Cloud-computing" et des applications mobiles, il est possible de trouver un service web répondant à presque tout besoin. De plus, les développeurs peuvent créer des applications complexes en combinant différents services indépendants, dont l’agencement et l’exécution peuvent être automatisés avec l’aide de langages d’orchestration. Cependant, la diversité des technologies et le manque de standardisation peuvent entraver la collaboration entre services. Un exemple de cette limitation est le cas de la gestion des photos avec des services tels que Flickr et Picasa, qui diffèrent non seulement sur la façon dont les photos sont organisées mais aussi sur les services qu’ils fournissent. L’hétérogénéité de ces deux services conduit à des problèmes d’interopérabilité, à savoir dans l’adaptation, l’intégration et la coordination. Nous proposons un framework pour aider à la résolution de ces problèmes, sous la forme d’une architecture qui intègre différents langages d’orchestration avec des fournisseurs de services hétérogènes autour d’un langage pivot. Comme langage pivot, nous proposons le langage d’orchestration Criojo qui implémente et étend le Heta-calcul, un calcul original associé à une machine chimique abstraite dédié à l’orchestration de services. En adoptant cette approche l’interopérabilité entre les services et les langages d’orchestration sera améliorée, facilitant ainsi le développement des services composites. Le haut niveau d’abstraction de Criojo pourrait permettre aux développeurs d’écrire des orchestrations très concises puisque les échanges de messages sont représentés d’une manière naturelle et intuitive. / With the emergence of cloud computing and mobile applications, it is possible to find a web service for almost everything. Moreover, developers can create complex applications by combining several independent services, whose arrangement and execution can be automated with the aid of orchestration languages. Nevertheless, the diversity of technologies and the lack of standardization can hinder the collaboration between services. An example of this limitation is the case of photo management with services such as Flickr and Picasa,which not only differ on the way photos are organized, but also in the services they provide. The heterogeneity of the two services leads to interoperability problems, namely adaptation, integration and coordination problems. We propose a framework for helping at the resolution of these issues, in the form of an architecture that integrates different orchestration languages with heterogeneous service providers around a pivot language. As a pivot language we propose an orchestration language based on the chemical programming paradigm. Concretely, this dissertation presents the language Criojo that implements and extends the Heta-calculus, an original calculus associated to a chemical abstract machine dedicated to service-oriented computing. The consequence of adopting this approach would bean improvement in the interoperability of services and orchestration languages, thus easing the development of composite services. The high level of abstraction of Criojo could allow developers to write very concise orchestrations since message exchanges are represented in a natural and intuitive way.
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HW/SW Codesign for the Xilinx Zynq Platform / HW/SW Codesign for the Xilinx Zynq PlatformViktorin, Jan January 2013 (has links)
This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.
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Automated event prioritization for security operation center using graph-based features and deep learningJindal, Nitika 06 April 2020 (has links)
A security operation center (SOC) is a cybersecurity clearinghouse responsible for monitoring, collecting and analyzing security events from organizations’ IT infrastructure and security controls. Despite their popularity, SOCs are facing increasing challenges and pressure due to the growing volume, velocity and variety of the IT infrastructure and security data observed on a daily basis. Due to the mixed performance of current technological solutions, e.g. intrusion detection system (IDS) and security information and event management (SIEM), there is an over-reliance on manual analysis of the events by human security analysts. This creates huge backlogs and slows down considerably the resolution of critical security events. Obvious solutions include increasing the accuracy and efficiency of crucial aspects of the SOC automation workflow, such as the event classification and prioritization. In the current thesis, we present a new approach for SOC event classification and prioritization by identifying a set of new machine learning features using graph visualization and graph metrics. Using a real-world SOC dataset and by applying different machine learning classification techniques, we demonstrate empirically the benefit of using the graph-based features in terms of improved classification accuracy. Three different classification techniques are explored, namely, logistic regression, XGBoost and deep neural network (DNN). The experimental evaluation shows for the DNN, the best performing classifier, area under curve (AUC) values of 91% for the baseline feature set and 99% for the augmented feature set that includes the graph-based features, which is a net improvement of 8% in classification performance. / Graduate
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Open Core Platform based on OpenRISC Processor and DE2-70 BoardLi, Xiang January 2011 (has links)
The trend of IP core reuse has been accelerating for years because of the increasing complexity in the System-on-Chip (SoC) designs. As a result, many IP cores of different types have been produced. Meanwhile, similar to the free software movement, an open core community has emerged because some designers choose to share their IP cores by using open source licenses. The open cores are growing fast due to their inherently attractive properties like accessible internal structure and usually no cost for license. Under this background, the master thesis was proposed by the company ENEA (Malmö/Lund branch), Sweden. It intended to evaluate the qualities of the open cores, as well as the difficulty and the feasibility of building an embedded platform by exclusively using the open cores. We contributed such an open core platform. It includes 5 open cores from the OpenCores organization: OpenRISC OR1200 processor, CONMAX WISHBONE interconnection IP core, Memory Controller IP core, UART16550, and General Purpose IOs (GPIO) IP core. More than that, we added the supports to DM9000A and WM8731 ICs for Ethernet and Audio features. On the software side, uC/OS-II RTOS and uC/TCP-IP stack have been ported to the platform. The OpenRISC toolchain for software development was tested. And a MP3 music player application has created to demonstrate the system. The open core platform is targeted to the Terasic’s DE2-70 board with ALTERA Cyclone II FPGA. It aims to have high flexibility for a wide range of embedded applications and at the same time with very low costs. The design of the thesis project are fully open and available online. We hope our work can be useful in the future as a starting point or a reference both for academic research or for commercial purposes.
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An Interconnection Network Topology Generation Scheme for Multicore SystemsPhanibhushana, Bharath 01 January 2013 (has links) (PDF)
Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade. Most common way of mapping applications to MPSoCs is by dividing the application into small tasks and representing them in the form of a task graph where the edges connecting the tasks represent the inter task communication. Task scheduling involves mapping task to processor cores so as to meet a specified deadline for the application/task graph. With increase in system complexity and application parallelism, task communication times are tending towards task execution times. Hence the NoC which forms the communication backbone for the cores plays a critical role in meeting the deadlines. In this thesis we present an approach to synthesize a minimal network connecting a set of cores in a MPSoC in the presence of deadlines. Given a task graph and a corresponding task to processor schedule, we have developed a partitioning methodology to generate an efficient interconnection network for the cores. We adopt a 2-phase design flow where we synthesize the network in first phase and in second phase we perform statistical analysis of the network thus generated. We compare our model with a simulated annealing based scheme, a static graph based greedy scheme and the standard mesh topology. The proposed solution offers significant area and performance benefits over the alternate solutions compared in this work.
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”Facebook har blivit lika självklart som att ha telefon” : Tre bibliotek i Umeåregionens arbete med sociala medier – en utvärderingSandström, Julia January 2013 (has links)
“Facebook has become as natural as having a phone” The use of social media in three libraries in the Umeå region – an evaluation Social media has come to be an integral part of people’s everyday life, as well as the business world in terms of communication and marketing. More and more libraries also embark in the use of social media, and the purpose of this study is to evaluate the use of social media in three libraries in the Umeå region. The libraries all use Facebook as their current, primary social media. Thus this study focuses partly on the analysis of the content on each library’s Facebook page, and partly on the experiences of the responsible librarians. The evaluation is based on a mix of existing tools in evaluating social media that are relevant in a library context. The posts on the Facebook pages are analyzed in three levels: activity, type of content and themes. This result is complemented with qualitative interviews with librarians who are working with social media at each library. One thing that is made clear in the study is the importance of having a plan for your use of social media as a library. The study also shows that posts that contain pictures are more likely to be “liked” or commented on than posts that consist of exclusively text or links to the library website. The most popular content, in regards to activity on the Facebook page, can also be categorized as “behind the scenes” material, such as posts about weather conditions.
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Compilation and Generation of Multi-Processor on a Chip Real-Time Embedded SystemsKlingler, Randall S. 10 July 2007 (has links) (PDF)
Current FPGA technology has advanced to the point that useful embedded System-on-Programmable-Chips (SoPC)s can now be designed. The Real Time Processor (RTP) project leverages the advances in FPGA technology with a system architecture that is customizable to specific real-time applications. The design and implementation of the framework for architecting such a system from ANSI-C code is presented. The Small Device C Compiler (SDCC) was retargeted to the RTP architecture and extended to produce a generator directive file. The RTPGen hardware generator was created to consume the directive file and produce a highly customized top-level structural VHDL file that can be synthesized and programmed onto an FPGA such as the Xilinx Spartan-3. Thus, an application specific multiprocessor real-time embedded system is realized from ANSI-C code.
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The whole is greater than the sum of its partsJasim, Tamara January 2013 (has links)
Helheten är större än summan av delarna – en fallstudie om hur olika faktorer kan påverka samtalsledares upplevelse av sin arbetssituation. Examensarbete i verksamhetsutveckling 30 högskolepoäng. Malmö högskola: Fakulteten för hälsa och samhälle, institutionen för Socionomprogrammet 2013. Denna studie undersöker och belyser hur samtalsledare som driver samtalsgrupper för unga pojkar upplever sin arbetssituation. Därför utgör följande frågeställningar ramen för denna studie: • Hur upplever samtalsledare sin arbetssituation i arbetet med att driva samtalsgrupper för unga pojkar? • Vilka faktorer kan påverka samtalsledarnas upplevelse av sin arbetssituation? För att besvara ovanstående frågeställningar har utformats en fallstudie där intervjuer med samtalsledare som driver samtalsgrupper för unga pojkar genomförts. Studien har genererat resultat som visar på att intervjuade samtalsledare upplever sig ha god förståelse för hur arbetet ska utföras och tillgång till resurser för att hantera olika situationer i arbetet och därför upplever en tillfredställelse med befintliga resurser i organisationen. Dock framgår att samtalsledare vars arbetsroll också innefattar organisatoriskt ansvar upplever behov av ökade ekonomiska resurser för att kunna arbeta med frågor rörande verksamhetsutveckling, metodutveckling och kvalitetssäkring. Vidare framgår att samtalsledarnas upplevelse av sin arbetssituation påverkas av personliga, organisatoriska och samhälleliga faktorer och att interaktionen mellan dessa har stor betydelse för hur samtalsledarna upplever sin arbetssituation. / The whole is greater than the sum of its parts - A case study of how different factors may affect communication leaders experience of his work situation Degree project in business development, 30 ECTS credits Malmö University: Faculty of health and society, Department of Social work program 2013 This study examines and illustrates how discussion leaders operating discussion groups for young boys experience their working situation. The following questions provided the framework for this study: • How do discussion leaders experience their work situation in efforts to run discussion groups for young men? • Which factors can affect the way discussion leaders experience their working situation? To answer the questions above have been designed a case study interviews with moderator who runs discussion groups for young men out. The study has generated results showing that interviewed discussion leaders experience that they have a good understanding of how the work is done and access to resources to cope with different situations at work and therefore experience a satisfaction with existing resources in the organization. However, it appears that discussion leaders whose work also includes organizational responsibility experience an increased need for financial resources in order to be able to work with matters related to business development, method development and quality assurance. Furthermore the study shows that the way discussion leaders experience their work situation is influenced by personal, organizational and societal factors and the interaction between them is of great importance for how discussion leaders experience their work situation.
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