In the industrial world, ensuring safety and operational efficiency, along with constant performance improvement, is of great importance. To achieve these goals, constant measurement of the parameters, such as vibration and sound, and monitoring of the system’s behavior are necessary. This master thesis will focus on the performance of the rotary parts of the machinery. Traditionally, human inspection and manual assessment are used to outline conclusions about the behavior and condition of the machine. Testing of the rotary parts involves analyzing audio signals by manual assessment. This thesis will focus on the vibrations produced by these parts and investigate ways to optimize the assessment of rotating systems. Utilizing the numerous advantages of embedded systems, in this case, STM32 microcontrollers, this master’s thesis explores signal processing methods such as the fast Fourier transform and Morlet wavelet transform. The detailed approach to applying both methods to analyze the data from the rotating system is described. It shows that both methods are good for detecting defects in rotating machinery, and the decision on which method to choose depends on the nature of the vibration signal as well as the nature of the faults that may occur. If machinery faults manifest in the form of periodic signals, the fast Fourier transform is a better option because it is more efficient and better for real-time systems, but for non-periodic faults, the Morlet wavelet transform is preferred. Additionally, through experimental analysis, this thesis gives new ideas on where to put sensors on rotating machines to get the best results. It shows that the sensors should be mounted close to the vibration source, on a flat surface and in the direction of the vibrations. This thesis lays a solid foundation for automating fault detection in rotating machinery, showing how to collect and analyze data that can be used for future implementation of machine learning models for predictive maintenance.

In the last two decades, Field Programmable Gate Arrays (FPGAs) have been rapidly developed from simple “glue-logic” to a powerful platform capable of implementing a System on Chip (SoC). Modern FPGAs achieve not only the high performance compared with General Purpose Processors (GPPs), thanks to hardware parallelism and dedication, but also better programming flexibility, in comparison to Application Specific Integrated Circuits (ASICs). Moreover, the hardware programming flexibility of FPGAs is further harnessed for both performance and manipulability, which makes Dynamic Partial Reconfiguration (DPR) possible. DPR allows a part or parts of a circuit to be reconfigured at run-time, without interrupting the rest of the chip’s operation. As a result, hardware resources can be more efficiently exploited since the chip resources can be reused by swapping in or out hardware tasks to or from the chip in a time-multiplexed fashion. In addition, DPR improves fault tolerance against transient errors and permanent damage, such as Single Event Upsets (SEUs) can be mitigated by reconfiguring the FPGA to avoid error accumulation. Furthermore, power and heat can be reduced by removing finished or idle tasks from the chip. For all these reasons above, DPR has significantly promoted Reconfigurable Computing (RC) and has become a very hot topic. However, since hardware integration is increasing at an exponential rate, and applications are becoming more complex with the growth of user demands, highlevel application design and low-level hardware implementation are increasingly separated and layered. As a consequence, users can obtain little advantage from DPR without the support of system-level middleware. To bridge the gap between the high-level application and the low-level hardware implementation, this thesis presents the important contributions towards a Reliable, Reconfigurable and Real-Time Operating System (R3TOS), which facilitates the user exploitation of DPR from the application level, by managing the complex hardware in the background. In R3TOS, hardware tasks behave just like software tasks, which can be created, scheduled, and mapped to different computing resources on the fly. The novel contributions of this work are: 1) a novel implementation of an efficient task scheduler and allocator; 2) implementation of a novel real-time scheduling algorithm (FAEDF) and two efficacious allocating algorithms (EAC and EVC), which schedule tasks in real-time and circumvent emerging faults while maintaining more compact empty areas. 3) Design and implementation of a faulttolerant microprocessor by harnessing the existing FPGA resources, such as Error Correction Code (ECC) and configuration primitives. 4) A novel symmetric multiprocessing (SMP)-based architectures that supports shared memory programing interface. 5) Two demonstrations of the integrated system, including a) the K-Nearest Neighbour classifier, which is a non-parametric classification algorithm widely used in various fields of data mining; and b) pairwise sequence alignment, namely the Smith Waterman algorithm, used for identifying similarities between two biological sequences. R3TOS gives considerably higher flexibility to support scalable multi-user, multitasking applications, whereby resources can be dynamically managed in respect of user requirements and hardware availability. Benefiting from this, not only the hardware resources can be more efficiently used, but also the system performance can be significantly increased. Results show that the scheduling and allocating efficiencies have been improved up to 2x, and the overall system performance is further improved by ~2.5x. Future work includes the development of Network on Chip (NoC), which is expected to further increase the communication throughput; as well as the standardization and automation of our system design, which will be carried out in line with the enablement of other high-level synthesis tools, to allow application developers to benefit from the system in a more efficient manner.

<p>Ова докторска теза описује и анализира приступ развоју Це компајлера за<br />наменске процесоре. Такав компајлер захтева имплементацију посебних<br />техника и алгоритама, претежно специфичних за нерегуларне процесорске<br />архитектуре, да би генерисао ефикасан код, и при том је потребно да<br />испуњава индустријске стандарде по питању робустности, разумљивости<br />кода, могућности одржавања и проширивости. У ту сврху је предложена<br />нова компајлерска инфраструктура над којом је имплементиран компајлер<br />за Cirrus Coyote 32 ДСП. Квалитет генерисаног кода поређен је са<br />квалитетом кода генерисног од стране већ постојећег компајлера за тај<br />процесор. Уједно, одређени елементи организације компајлера су<br />упоређени са популарним компајлерима отвореног кода GCC и LLVM.</p> / <p>Ova doktorska teza opisuje i analizira pristup razvoju Ce kompajlera za<br />namenske procesore. Takav kompajler zahteva implementaciju posebnih<br />tehnika i algoritama, pretežno specifičnih za neregularne procesorske<br />arhitekture, da bi generisao efikasan kod, i pri tom je potrebno da<br />ispunjava industrijske standarde po pitanju robustnosti, razumljivosti<br />koda, mogućnosti održavanja i proširivosti. U tu svrhu je predložena<br />nova kompajlerska infrastruktura nad kojom je implementiran kompajler<br />za Cirrus Coyote 32 DSP. Kvalitet generisanog koda poređen je sa<br />kvalitetom koda generisnog od strane već postojećeg kompajlera za taj<br />procesor. Ujedno, određeni elementi organizacije kompajlera su<br />upoređeni sa popularnim kompajlerima otvorenog koda GCC i LLVM.</p> / <p>This PhD thesis describes and analyses an approach to development of C<br />language compiler for embedded processors. That kind of compiler requires<br />implementation of special techniques and algorithms, mostly specific for<br />irregular processor architectures, in order to be able to generate efficient<br />code, whereas still meeting industrial strength standard by beeing robust,<br />understandable, maintainable, and extensible. For this purpose the new<br />compiler insfrastructure is proposed and on top of it a compiler for Cirrus<br />Logic Coyote 32 DSP is built. Quality of the code generated by that compiler<br />is compared with code generated by the previous compiler for the same<br />processor architecture. Some elements of the compiler design are also<br />compared to popular open source compilers GCC and LLVM.</p>

A crescente demanda por Veículos Aéreos Não Tripulados (VANT) tem sido objeto de preocupação por parte das organizações internacionais responsáveis pela segurança do espaço aéreo. O uso de VANT em condições restritas tem sido realizado pelos interessados e envolvidos, mas para que o VANT seja economicamente viável, há a necessidade de regulamentação ainda não existente para sua integração segura no Espaço Aéreo Controlado e Não Segregado. Em função dessa demanda não atendida, nesta Tese foi desenvolvido um método (Safety-VANT) que avalia a segurança crítica da condução do VANT, tarefa realizada por um Sistema Autônomo de Pilotagem. O desenvolvimento do Método Safety-VANT tem como missão fornecer aos órgãos reguladores, assim como aos desenvolvedores de VANT, meios de quantificar a avaliação de segurança na navegabilidade aérea dessas aeronaves. Uma hipótese considerada para o método é a de que o hardware e software (aviônicos, fuselagem, sensores e atuadores) do VANT estejam previamente avaliados e certificados pelos mesmos procedimentos e regras aplicáveis para os equipamentos de aeronaves tripuladas. Essa hipótese permitiu que o desenvolvimento do método de avaliação de segurança Safety-VANT fosse direcionado para avaliar a capacidade de comando autônomo de um VANT para voar, navegar e comunicar de acordo com as regras do sistema de gerenciamento e controle do tráfego aéreo. A aplicação do Safety-VANT foi exercitada sob um VANT hipotético definido como sendo capaz de voar, navegar e se comunicar com o Controle de Tráfego Aéreo e que tenha os equipamentos e estrutura da aeronave (fuselagem) que o constitui, devidamente certificados. Adicionalmente são realizadas considerações sobre como implantar a utilização do Safety-VANT no desenvolvimento de VANT Autônomo com a missão de ser integrado no Espaço Aéreo. / The growing demand for unmanned aerial vehicles (UAV) has been a subject of concern on the part of international organizations responsible for airspace safety. UAV has been used by stakeholders in strict conditions, but for UAV to become economically viable, it is necessary to issue regulations that still do not exist for safe integration in the controlled non-segregated airspace. In the light of this unattended demand, a method (Safety-VANT) was developed in this Thesis to evaluate the critical safety of UAV conduction, a task performed by a Piloting Autonomous System. The development of the Safety-VANT method aims to provide UAV regulators and developers, means of quantifying the safety assessment in the aircraft airworthiness. A hypothesis used in the method considers that the UAV hardware and software (avionics, fairing, sensors and actuators) are previously evaluated and certified by the same procedures and rules applicable to manned aircraft equipment. This hypothesis allowed the Safety-VANT - the developed safety assessment method - to evaluate the ability of an autonomous command embedded in an UAV to fly, to navigate and to communicate, according to the management of air navigation system rules. The Safety-VANT application was exercised under a hypothetical UAV set to being able to fly, to navigate and to communicate with Air Traffic Control and it has the equipment and the certified aircraft structure (fairing). In addition, considerations are performed for deploying the use of Safety-VANT in autonomous UAV development to integrate it into the Airspace.

A aplicação eficiente de agrotóxicos é um desafio na produção agrícola, mesmo considerando os avanços com a agricultura de precisão. O efeito deriva é o principal responsável pela ineficiência no controle das pragas ou doenças, pelo desperdício de recursos e pela contaminação ambiental. Para minimizar a deriva é essencial conhecer as condições ambientais como vento, temperatura e umidade. Esta pesquisa propõe o uso das redes de sensores sem fio como sistema de monitoramento ambiental e de suporte ao processo de pulverização agrícola, especialmente a pulverização executada por aeronave. São propostas três funcionalidades para o sistema: avaliação das condições ambientais, verificando se as condições estão apropriadas para a pulverização, buscando minimizar a ocorrência da deriva; suporte na definição e manutenção da rota do veículo pulverizador por meio dos dados do vento, de modo a efetuar ajustes na rota de pulverização e manter a aplicação do defensivo agrícola na área alvo; e a avaliação da eficácia da pulverização por meio dos dados da deposição do produto pulverizado coletados pela rede de sensores. Para viabilizar a utilização das redes de sensores sem fio no controle da deriva é proposto um protocolo de roteamento de dados que visa garantir a coleta dos dados pelos nós e a entrega para o veículo pulverizador, mesmo sendo ele um avião e se deslocando em alta velocidade. Para demonstrar a viabilidade do sistema proposto, foi desenvolvido um sistema de simulação computacional que considera os aspectos das redes de sensores sem fio e as características do protocolo de roteamento proposto. Os resultados demonstraram sua viabilidade, demonstrando que as redes de sensores sem fio podem ser utilizadas como suporte em um sistema de controle da deriva, incrementando a qualidade da pulverização, reduzindo custos e a contaminação ambiental. / The efficient application of low cost pesticides is a challenge for agricultural production. Pesticide drift is the major cause of money loss, inefficiency in crop disease control, and environmental contamination in the crop spraying process. At the time of application, it is essential to know the environmental conditions, such as wind, temperature and humidity to minimize contamination by pesticide drift. This study proposes the use of wireless sensor networks in a support and control system for crop spraying, especially in aircraft application methods. Three system functionalities are proposed: In the first case, the sensor network evaluates environmental data at the time of application to notify the user if the environmental conditions are suitable for continuing with the application. The second case evaluates the wind speed and its direction to suggest corrections in the path of a spray vehicle. Due to this alteration in the vehicle path, the pesticide will be applied only in the appropriate area. The final case involves collecting data samples and analyzing the quality of the spraying operation by evaluating the deposition of pesticide over the crop. This work proposes a new routing data protocol to make possible the use of wireless sensor networks in aerial crop spraying. It ensures that the sensor node data will be delivered to the sink node. Through computer simulations, wireless sensor networks are shown to be useful in crop spraying to minimize and to control pesticide drift, to improve the quality of application, to reduce environmental contamination and to reduce costs and the duration of the application operation.

Dans la société moderne, le stress s’avère un problème omniprésent. Un stress permanent peut entraîner divers problèmes mentaux et physiques notamment pour des personnes confrontées à des situations d'urgence comme par exemple des pompiers en intervention: il peut modifier leurs actions et les mettre en danger. Par conséquent, dans ce contexte, il est pertinent de chercher à évaluer le stress de la personne. Sur la base de cette idée, a été proposé le projet Psypocket qui vise à concevoir un système portable capable d'analyser précisément l'état de stress d'une personne en fonction de ses modifications physiologiques, psychologiques et comportementales, puis de proposer des solutions de rétroaction pour réguler cet état. Cette thèse s’inscrit dans le cadre du projet Psypocket. Nous y discutons de la faisabilité et de l'intérêt de la reconnaissance du stress à partir de données hétérogènes. Non seulement les signaux physiologiques, tels que l'électrocardiographie (ECG), l'élecchtromyographie (EMG) et l'activité électrodermale (EDA), mais aussi le temps de réaction (RT) sont adoptés pour discriminer différents états de stress d'une personne. Pour cela nous proposons une approche basée sur un classifieur SVM (Machine à Vecteurs de Support). Les résultats obtenus montrent que le temps de réaction peut-être un moyen d’estimation du niveau de stress de l’individu en complément ou non des signaux physiologiques. En outre, nous discutons de la faisabilité d'un système embarqué à même de réaliser la chaîne globale de traitement des signaux. Cette thèse contribue donc à la conception d’un système portable de reconnaissance du stress d'une personne en temps réel en adoptant des données hétérogènes, en l’occurrence les signaux physiologiques et le temps de réaction / In modern society, the stress of an individual has been found to be a common problem. Continuous stress can lead to various mental and physical problems and especially for the people who always face emergency situations (e.g., fireman): it may alter their actions and put them in danger. Therefore, it is meaningful to provide the assessment of the stress of an individual. Based on this idea, the Psypocket project is proposed which is aimed at making a portable system able to analyze accurately the stress state of an individual based on his physiological, psychological and behavioural modifications. It should then offer solutions for feedback to regulate this state.The research of this thesis is an essential part of the Psypocket project. In this thesis, we discuss the feasibility and the interest of stress recognition from heterogeneous data. Not only physiological signals, such as Electrocardiography (ECG), Electromyography (EMG) and Electrodermal activity (EDA), but also reaction time (RT) are adopted to recognize different stress states of an individual. For the stress recognition, we propose an approach based on a SVM classifier (Support Vector Machine). The results obtained show that the reaction time can be used to estimate the level of stress of an individual in addition or not to the physiological signals. Besides, we discuss the feasibility of an embedded system which would realize the complete data processing. Therefore, the study of this thesis can contribute to make a portable system to recognize the stress of an individual in real time by adopting heterogeneous data like physiological signals and RT

Le travail présenté dans ce mémoire concerne une méthode de conception sûre de systèmes(COTS). Un COTS est un composant matériel ou logiciel générique qui est naturellement conçu pour être réutilisable et cela se traduit par une forme de flexibilité dans la mise en oeuvre de sa fonctionnalité : en clair, une même fonction peut être réalisée par un ensemble (potentiellement infini) de scénarios différents, tous réalisables par le COTS. La complexité grandissante des fonctions implémentées fait que ces situations sont très difficiles à anticiper d’une part, et encore plus difficiles à éviter par un codage correct. Réaliser manuellement une fonction composite correcte sur un système de taille industrielle, s’avère être très coûteuse. Elle nécessite une connaissance approfondie du comportement des COTS assemblés. Or cette connaissance est souvent manquante, vu qu’il s’agit de composants acquis, ou développés par un tiers, et dont la documentation porte sur la description de leur fonction et non sur sa mise en IJuvre. Par ailleurs, il arrive souvent que la correction manuelle d’une faute engendre une ou plusieurs autres fautes, provoquant un cercle vicieux difficile à maîtriser. En plus, le fait de modifier le code d’un composant diminue l’avantage lié à sa réutilisation. C’est dans ce contexte que nous proposons l’utilisation de la technique de synthèse du contrôleur discret (SCD) pour générer automatiquement du code de contrôle commande correct par construction. Cette technique produit des composants, nommés contrôleurs, qui agissent en contraignant le comportement d’un (ou d’un assemblage de) COTS afin de garantir si possible la satisfaction d’une exigence fonctionnelle. La méthode que nous proposons possède plusieurs étapes de conception. La première étape concerne la formalisation des COTS et des propriété de sûreté et de vivacité (P) en modèles automate à états et/ou en logique temporelle. L’étape suivante concerne la vérification formelle du modèle d’un(des) COTS pour l’ensemble des propriétés (P). Cette étape découvrir les états de violation des propriétés (P) appelés états d’erreur. La troisième étape concerne la correction automatique des erreurs détectées en utilisant la technique SCD. Dans cette étape génère on génère un composant correcteur qui sera assemblé au(x) COTS original(aux) pour que leur comportement général respecte les propriétés souhaitées. L’étape suivante concerne la vérification du système contrôlé pour un ensemble de propriétés de vivacité pour assurer la passivité du contrôleur et la vivacité du système. En fin, une étape de simulation est proposée pour observer le comportement du système pour quelque scénarios intéressent par rapport à son implémentation finale. / This PhD dissertation contributes to the safe design of COTS-based control-command embedded systems. Due to design constraints bounding delays, costs and engineering resources, component re-usability has become a key issue in embedded design. Our proposal is a design method which ensures correction of COTS-based designs. This method uses in synergy a number of design techniques and tools. It starts from modeling of the COTS components which are stored in a generic COTS library, and ends with a design of the global control-command system, verified to be free of errors and ready to be implemented over a hardware chip such as an ASIC or an FPGA "Field Programmable Gate Array". The designer starts by modeling the temporal and logical local preconditions and postconditions of each COTS component, then the global pre/post conditions of the assembly which are not necessary a simple combination of local properties. He models also a list of properties that must be satisfied by the assembly. Any violation of these properties is defined as a design error. Then, by using the model checking approach the model of the assembly is verified against the predefined local and global properties. Some design errors can be corrected automatically through the Discrete Controller Synthesis method (DCS), others however must be manually corrected. After the correction step, the controlled control-command system is verified. Finally a global simulation step is proposed in order to perform a system-level verification beyond the capabilities of available formal tools. We apply the method on two different systems, one concerns transferring data from senders to receivers through FIFO unit, the other is controlcommand system of a train passengers’ access.

A crescente demanda por Veículos Aéreos Não Tripulados (VANT) tem sido objeto de preocupação por parte das organizações internacionais responsáveis pela segurança do espaço aéreo. O uso de VANT em condições restritas tem sido realizado pelos interessados e envolvidos, mas para que o VANT seja economicamente viável, há a necessidade de regulamentação ainda não existente para sua integração segura no Espaço Aéreo Controlado e Não Segregado. Em função dessa demanda não atendida, nesta Tese foi desenvolvido um método (Safety-VANT) que avalia a segurança crítica da condução do VANT, tarefa realizada por um Sistema Autônomo de Pilotagem. O desenvolvimento do Método Safety-VANT tem como missão fornecer aos órgãos reguladores, assim como aos desenvolvedores de VANT, meios de quantificar a avaliação de segurança na navegabilidade aérea dessas aeronaves. Uma hipótese considerada para o método é a de que o hardware e software (aviônicos, fuselagem, sensores e atuadores) do VANT estejam previamente avaliados e certificados pelos mesmos procedimentos e regras aplicáveis para os equipamentos de aeronaves tripuladas. Essa hipótese permitiu que o desenvolvimento do método de avaliação de segurança Safety-VANT fosse direcionado para avaliar a capacidade de comando autônomo de um VANT para voar, navegar e comunicar de acordo com as regras do sistema de gerenciamento e controle do tráfego aéreo. A aplicação do Safety-VANT foi exercitada sob um VANT hipotético definido como sendo capaz de voar, navegar e se comunicar com o Controle de Tráfego Aéreo e que tenha os equipamentos e estrutura da aeronave (fuselagem) que o constitui, devidamente certificados. Adicionalmente são realizadas considerações sobre como implantar a utilização do Safety-VANT no desenvolvimento de VANT Autônomo com a missão de ser integrado no Espaço Aéreo. / The growing demand for unmanned aerial vehicles (UAV) has been a subject of concern on the part of international organizations responsible for airspace safety. UAV has been used by stakeholders in strict conditions, but for UAV to become economically viable, it is necessary to issue regulations that still do not exist for safe integration in the controlled non-segregated airspace. In the light of this unattended demand, a method (Safety-VANT) was developed in this Thesis to evaluate the critical safety of UAV conduction, a task performed by a Piloting Autonomous System. The development of the Safety-VANT method aims to provide UAV regulators and developers, means of quantifying the safety assessment in the aircraft airworthiness. A hypothesis used in the method considers that the UAV hardware and software (avionics, fairing, sensors and actuators) are previously evaluated and certified by the same procedures and rules applicable to manned aircraft equipment. This hypothesis allowed the Safety-VANT - the developed safety assessment method - to evaluate the ability of an autonomous command embedded in an UAV to fly, to navigate and to communicate, according to the management of air navigation system rules. The Safety-VANT application was exercised under a hypothetical UAV set to being able to fly, to navigate and to communicate with Air Traffic Control and it has the equipment and the certified aircraft structure (fairing). In addition, considerations are performed for deploying the use of Safety-VANT in autonomous UAV development to integrate it into the Airspace.

A aplicação eficiente de agrotóxicos é um desafio na produção agrícola, mesmo considerando os avanços com a agricultura de precisão. O efeito deriva é o principal responsável pela ineficiência no controle das pragas ou doenças, pelo desperdício de recursos e pela contaminação ambiental. Para minimizar a deriva é essencial conhecer as condições ambientais como vento, temperatura e umidade. Esta pesquisa propõe o uso das redes de sensores sem fio como sistema de monitoramento ambiental e de suporte ao processo de pulverização agrícola, especialmente a pulverização executada por aeronave. São propostas três funcionalidades para o sistema: avaliação das condições ambientais, verificando se as condições estão apropriadas para a pulverização, buscando minimizar a ocorrência da deriva; suporte na definição e manutenção da rota do veículo pulverizador por meio dos dados do vento, de modo a efetuar ajustes na rota de pulverização e manter a aplicação do defensivo agrícola na área alvo; e a avaliação da eficácia da pulverização por meio dos dados da deposição do produto pulverizado coletados pela rede de sensores. Para viabilizar a utilização das redes de sensores sem fio no controle da deriva é proposto um protocolo de roteamento de dados que visa garantir a coleta dos dados pelos nós e a entrega para o veículo pulverizador, mesmo sendo ele um avião e se deslocando em alta velocidade. Para demonstrar a viabilidade do sistema proposto, foi desenvolvido um sistema de simulação computacional que considera os aspectos das redes de sensores sem fio e as características do protocolo de roteamento proposto. Os resultados demonstraram sua viabilidade, demonstrando que as redes de sensores sem fio podem ser utilizadas como suporte em um sistema de controle da deriva, incrementando a qualidade da pulverização, reduzindo custos e a contaminação ambiental. / The efficient application of low cost pesticides is a challenge for agricultural production. Pesticide drift is the major cause of money loss, inefficiency in crop disease control, and environmental contamination in the crop spraying process. At the time of application, it is essential to know the environmental conditions, such as wind, temperature and humidity to minimize contamination by pesticide drift. This study proposes the use of wireless sensor networks in a support and control system for crop spraying, especially in aircraft application methods. Three system functionalities are proposed: In the first case, the sensor network evaluates environmental data at the time of application to notify the user if the environmental conditions are suitable for continuing with the application. The second case evaluates the wind speed and its direction to suggest corrections in the path of a spray vehicle. Due to this alteration in the vehicle path, the pesticide will be applied only in the appropriate area. The final case involves collecting data samples and analyzing the quality of the spraying operation by evaluating the deposition of pesticide over the crop. This work proposes a new routing data protocol to make possible the use of wireless sensor networks in aerial crop spraying. It ensures that the sensor node data will be delivered to the sink node. Through computer simulations, wireless sensor networks are shown to be useful in crop spraying to minimize and to control pesticide drift, to improve the quality of application, to reduce environmental contamination and to reduce costs and the duration of the application operation.

Die Java-Plattform bietet viele Vorteile für die schnelle Entwicklung komplexer Software. Für die Ausführung des Java-Bytecodes auf eingebetteten Systemen eignen sich insbesondere Java-(Bytecode)-Prozessoren, die den Java-Bytecode als nativen Befehlssatz unterstützen. Die vorliegende Arbeit untersucht detailliert die Gestaltung einer Mehrkernarchitektur für Java-Prozessoren zur effizienten Nutzung der auf Thread-Ebene ohnehin vorhandenen Parallelität eines Java-Programms. Für die Funktionalitäts- und Leistungsbewertung eines Prototyps wird eine eigene Trace-Architektur eingesetzt. Es wird eine hohe Leistungssteigerung bei nur geringem zusätzlichem Hardwareaufwand erzielt sowie eine höhere Leistung als bekannte alternative Ansätze erreicht.