Volterra Series (VS) is often used in the analysis of mildly nonlinear circuits. In this approach, nonlinear circuit analysis is converted into the analysis of a series of linear circuits. The main benefit of this approach is that linear circuit analysis is well established and direct frequency domain analysis of a nonlinear circuit becomes possible. Sensitivity analysis is useful in comparing the quality of two designs and the evaluation of gradient, Jacobian or Hessian matrices, in analog Computer Aided Design. This thesis presents, for the first time, the sensitivity analysis of mildly nonlinear circuits in the frequency domain as an extension of the VS approach. To overcome efficiency limitation due to multiple mixing effects, Nonlinear Transfer Matrix (NTM) is introduced. It is the first explicit analytical representation of the complicated multiple mixing effects. The application of NTM in sensitivity analysis is capable of two orders of magnitude speedup. Per-element distortion decomposition determines the contribution towards the total distortion from an individual nonlinearity. It is useful in design optimization, symbolic simplification and nonlinear model reduction. In this thesis, a numerical distortion decomposition technique is introduced which combines the insight of traditional symbolic analysis with the numerical advantages of SPICE like simulators. The use of NTM leads to an efficient implementation. The proposed method greatly extends the size of the circuit and the complexity of the transistor model over what previous approaches could handle. For example, industry standard compact model, such as BSIM3V3 [35] was used for the first time in distortion analysis. The decomposition can be achieved at device, transistor and block level, all with device level accuracy. The theories have been implemented in a computer program and validated on examples. The proposed methods will leverage the performance of present VS based distortion analysis to the next level.

Les systèmes dynamiques présentent des comportements temporels qui peuvent être exprimés sous diverses formes séquentielles telles que des signaux, des ondes, des séries chronologiques et des suites d'événements. Détecter des motifs sur de tels comportements temporels est une tâche fondamentale pour comprendre et évaluer ces systèmes. Étant donné que de nombreux comportements du système impliquent certaines caractéristiques temporelles, le besoin de spécifier et de détecter des motifs de comportements qui implique des exigences de synchronisation, appelées motifs temporisés, est évidente.Cependant, il s'agit d'une tâche non triviale due à un certain nombre de raisons, notamment la concomitance des sous-systèmes et la densité de temps.La contribution principale de cette thèse est l'introduction et le développement du filtrage par motif temporisé, c'est-à-dire l'identification des segments d'un comportement donné qui satisfont un motif temporisé. Nous proposons des expressions rationnelles temporisées (TRE) et la logique de la boussole métrique (MCL) comme langages de spécification pour motifs temporisés. Nous développons d'abord un nouveau cadre qui abstraite le calcul des aspects liés au temps appelé l'algèbre des relations temporisées. Ensuite, nous fournissons des algorithmes du filtrage hors ligne pour TRE et MCL sur des comportements à temps dense à valeurs discrètes en utilisant ce cadre et étudions quelques extensions pratiques.Il est nécessaire pour certains domaines d'application tels que le contrôle réactif que le filtrage par motif doit être effectué pendant l'exécution réelle du système. Pour cela, nous fournissons un algorithme du filtrage en ligne pour TREs basé sur la technique classique des dérivées d'expressions rationnelles. Nous croyons que la technique sous-jacente qui combine les dérivées et les relations temporisées constitue une autre contribution conceptuelle majeure pour la recherche sur les systèmes temporisés.Nous présentons un logiciel libre Montre qui implémente nos idées et algorithmes. Nous explorons diverses applications du filtrage par motif temporisé par l'intermédiaire de plusieurs études de cas. Enfin, nous discutons des orientations futures et plusieurs questions ouvertes qui ont émergé à la suite de cette thèse. / Dynamical systems exhibit temporal behaviors that can be expressed in various sequential forms such as signals, waveforms, time series, and event sequences. Detecting patterns over such temporal behaviors is a fundamental task for understanding and assessing these systems. Since many system behaviors involve certain timing characteristics, the need to specify and detect patterns of behaviors that involves timing requirements, called timed patterns, is evident. However, this is a non-trivial task due to a number of reasons including the concurrency of subsystems and density of time.The key contribution of this thesis is in introducing and developing emph{timed pattern matching}, that is, the act of identifying segments of a given behavior that satisfy a timed pattern. We propose timed regular expressions (TREs) and metric compass logic (MCL) as timed pattern specification languages. We first develop a novel framework that abstracts the computation of time-related aspects called the algebra of timed relations. Then we provide offline matching algorithms for TRE and MCL over discrete-valued dense-time behaviors using this framework and study some practical extensions.It is necessary for some application areas such as reactive control that pattern matching needs to be performed during the actual execution of the system. For that, we provide an online matching algorithm for TREs based on the classical technique of derivatives of regular expressions. We believe the underlying technique that combines derivatives and timed relations constitutes another major conceptual contribution for timed systems research.Furthermore, we present an open-source tool Montre that implements our ideas and algorithms. We explore diverse applications of timed pattern matching over several case studies using Montre. Finally we discuss future directions and several open questions emerged as a result of this thesis.

Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A radiação ionizante presente no espaço pode afetar o funcionamento das estruturas MOS, sendo que um dos parâmetros mais prejudicados é a tensão de limiar (Threshold Voltage). Em virtude da diferença nos mecanismos de aprisionamento de cargas nos óxidos dos transistores do tipo N e do tipo P, esses dois dispositivos exibem comportamentos distintos à medida que a dose acumulada aumenta referente à tensão de limiar. Por isso, foram investigados os comportamentos de dois tipos de amplificadores que podem ser ditos complementares entre si. Nesse contexto, através de simulações SPICE desvios na tensão de limiar foram promovidos através da injeção direta no arquivo de parâmetros da tecnologia considerada. Com isso, um conjunto de simulações foi feito para gerar a estimativa da tendência de comportamento de parâmetros que qualificam o desempenho dos amplificadores operacionais, como é o caso do produto ganho largura de banda (GB), ganho DC e THD (Total Harmonic Distortion). Nesse sentido, foi possível compreender os mecanismos associados à degradação de desempenho e concluir qual das duas arquiteturas pode apresentar melhor desempenho relacionado à TID. / This work studies the effects of Total Ionizing Dose (TID) in operational amplifiers as well as in their basics building blocks. The radiation from space may affect functionality of MOS structures. One the most affected parameters is the threshold voltage. Due to the difference between N-type and P-type transistors related to the mechanism of charge trapping into the oxides, these two devices exhibit different behaviors, related to the threshold voltage parameter according to accumulated dose. Therefore, this work investigates the behavior of two counterpart operational amplifiers. In this context, by means of SPICE simulations, threshold deviations are injected into the transistors by modifying the technology models of the devices. Thus, a set of simulations was performed in order to generate an estimative of tendency for some of performance parameters of operational amplifiers, such as: the gain-bandwidth product (GB), DC gain, THD (Total Harmonic Distortion). In this sense, it was possible to understand the mechanisms associated to performance degradation and also, to conclude which of both architectures is more robust related to TID.

Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A radiação ionizante presente no espaço pode afetar o funcionamento das estruturas MOS, sendo que um dos parâmetros mais prejudicados é a tensão de limiar (Threshold Voltage). Em virtude da diferença nos mecanismos de aprisionamento de cargas nos óxidos dos transistores do tipo N e do tipo P, esses dois dispositivos exibem comportamentos distintos à medida que a dose acumulada aumenta referente à tensão de limiar. Por isso, foram investigados os comportamentos de dois tipos de amplificadores que podem ser ditos complementares entre si. Nesse contexto, através de simulações SPICE desvios na tensão de limiar foram promovidos através da injeção direta no arquivo de parâmetros da tecnologia considerada. Com isso, um conjunto de simulações foi feito para gerar a estimativa da tendência de comportamento de parâmetros que qualificam o desempenho dos amplificadores operacionais, como é o caso do produto ganho largura de banda (GB), ganho DC e THD (Total Harmonic Distortion). Nesse sentido, foi possível compreender os mecanismos associados à degradação de desempenho e concluir qual das duas arquiteturas pode apresentar melhor desempenho relacionado à TID. / This work studies the effects of Total Ionizing Dose (TID) in operational amplifiers as well as in their basics building blocks. The radiation from space may affect functionality of MOS structures. One the most affected parameters is the threshold voltage. Due to the difference between N-type and P-type transistors related to the mechanism of charge trapping into the oxides, these two devices exhibit different behaviors, related to the threshold voltage parameter according to accumulated dose. Therefore, this work investigates the behavior of two counterpart operational amplifiers. In this context, by means of SPICE simulations, threshold deviations are injected into the transistors by modifying the technology models of the devices. Thus, a set of simulations was performed in order to generate an estimative of tendency for some of performance parameters of operational amplifiers, such as: the gain-bandwidth product (GB), DC gain, THD (Total Harmonic Distortion). In this sense, it was possible to understand the mechanisms associated to performance degradation and also, to conclude which of both architectures is more robust related to TID.

Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A radiação ionizante presente no espaço pode afetar o funcionamento das estruturas MOS, sendo que um dos parâmetros mais prejudicados é a tensão de limiar (Threshold Voltage). Em virtude da diferença nos mecanismos de aprisionamento de cargas nos óxidos dos transistores do tipo N e do tipo P, esses dois dispositivos exibem comportamentos distintos à medida que a dose acumulada aumenta referente à tensão de limiar. Por isso, foram investigados os comportamentos de dois tipos de amplificadores que podem ser ditos complementares entre si. Nesse contexto, através de simulações SPICE desvios na tensão de limiar foram promovidos através da injeção direta no arquivo de parâmetros da tecnologia considerada. Com isso, um conjunto de simulações foi feito para gerar a estimativa da tendência de comportamento de parâmetros que qualificam o desempenho dos amplificadores operacionais, como é o caso do produto ganho largura de banda (GB), ganho DC e THD (Total Harmonic Distortion). Nesse sentido, foi possível compreender os mecanismos associados à degradação de desempenho e concluir qual das duas arquiteturas pode apresentar melhor desempenho relacionado à TID. / This work studies the effects of Total Ionizing Dose (TID) in operational amplifiers as well as in their basics building blocks. The radiation from space may affect functionality of MOS structures. One the most affected parameters is the threshold voltage. Due to the difference between N-type and P-type transistors related to the mechanism of charge trapping into the oxides, these two devices exhibit different behaviors, related to the threshold voltage parameter according to accumulated dose. Therefore, this work investigates the behavior of two counterpart operational amplifiers. In this context, by means of SPICE simulations, threshold deviations are injected into the transistors by modifying the technology models of the devices. Thus, a set of simulations was performed in order to generate an estimative of tendency for some of performance parameters of operational amplifiers, such as: the gain-bandwidth product (GB), DC gain, THD (Total Harmonic Distortion). In this sense, it was possible to understand the mechanisms associated to performance degradation and also, to conclude which of both architectures is more robust related to TID.

The topic of the master´s thesis are voltage and current reference sources. There is detailed description of current and voltage references, which are basic building blocks of many analog circuits, in the theoretical part. Next part of the master´s thesis is the design of a voltage reference source, the design of a voltage reference generating two voltages and a current reference source. The correct function of all circuits have been verified using simulations, especially dependence of the output voltage or current on supply voltage or dependence of the output voltage or current when the ambient temperature is changed.

De nos jours, la conception des systèmes sur puce devient de plus en plus complexe, et requiert des densités de mémoire sans cesse grandissantes. Pour ce faire, une forte miniaturisation des nœuds technologiques s’opère. Les mémoires non-volatiles résistives, tels que les RRAM, PC-RAM ou MRAM se présentent comme des alternatives technologiques afin d'assurer à la fois une densité suffisante et des faibles contraintes en surface, en latence, et en consommation à l’échelle nanométrique. Cependant, la variabilité croissante de ces cellules mémoires ainsi que des circuits en périphérie, tels que des circuits de lecture, est un problème majeur à prendre en considération. Cette thèse consiste en une étude détaillée et une aide à la compréhension de la problématique de variabilité appliquée aux circuits de lecture pour mémoires résistives. Elle propose des solutions d’amélioration de la fiabilité de lecture de ces mémoires. Pour ce faire, diverses études ont été réalisées : revue générale des solutions existantes d’amélioration du rendement de lecture, au niveau circuit et système ; développement d’un modèle statistique évaluant la contribution à la marge de lecture de la variabilité de chaque composante du chemin de lecture de la mémoire résistive ; analyse, caractérisation, modélisation et optimisation de l’offset d’un amplificateur de lecture dynamique pour mémoires résistives ; proposition d’architecture d’amplificateur de lecture permettant un rapport signal à offset optimum. / Nowadays, Systems on chip (SoCs) conception is becoming more and more complex and demand an ever-increasing amount of memory capacity. This leads to aggressive bit cell technology scaling. Nonvolatile resistive memories (PC-RAM, RRAM, MRAM) are promising technologic alternatives to ensure both high density, low power consumption, low area and low latencies. However, scaling lead to significant memory cell and/or memory periphery variability. This thesis aims to address variability issues in read circuitries of resistive memories and propose solutions for read yield enhancement of these memories. To this end, several sub-studies were achieved: overall review of the existing solutions for read yield enhancement, at both circuit and system level; development of a statistical model evaluating the contributions to read margin of the variability of each component of the resistive memory sensing path; analysis, characterization modelling and optimization of the offset of one particular dynamic sense amplifier for resistive memories; proposal of a sense amplifier architecture that features an optimum signal to offset ratio.

Le travail réalisé lors de cette thèse s’inscrit dans le projet de création d’un calorimètre électromagnétique pour le futur International Linear Collider (ILC) au sein de la collaboration CALICE. Le calorimètre est dit ultra-granulaire du fait du grand nombre de pixels de détection : environ 82 millions dans le calorimètre final complet. C’est ce nombre élevé de détecteurs à lire qui a conduit au développement de circuits intégrés dédiés à cette tâche, l’usage d’électronique classique n’étant pas possible dans ce cas du fait de contraintes dimensionnelles. Les travaux démarrent par l’étude de la puce SKIROC2, développée par le laboratoire Omega, qui est l’état de l’art de l’ASIC de lecture pour ce projet. Les performances sur carte de test et dans l’environnement du détecteur ont été mesurées, ce qui a permis de tirer certaines conclusions sur les forces et les faiblesses de SKIROC2. Après cette étude, le travail a été le développement d’un nouvel ASIC de lecture se basant sur SKIROC2. L’objectif étant de préserver les forces de SKIROC2 tout en tentant d’en corriger les faiblesses. Le nouvel ASIC a été conçu dans une technologie tout juste disponible au moment de la conception. Il a donc tout fallu redessiner en repartant de zéro. Il s’agit en cela de building blocks plus que d’un véritable ASIC de lecture. Trois structures de préamplificateurs de charge ont été testées, l’architecture générale et le fonctionnement d’un canal de lecture étant largement inspirés de SKIROC2. / This work takes place in the design project of the electromagnetic calorimeter for the future International Linear Collider (ILC) within the CALICE collaboration. The final calorimeter will be made of 82 million of PIN diodes; this is where the term “high granularity” comes from. The need for a read-out ASIC is a consequence of this high number of detectors, knowing that the dimensions of the electromagnetic calorimeter are a big constraint: the standard electronics is not an option. This work starts from an existing ASIC called SKIROC2. This state-of-the-art read-out chip has been designed by the Omega laboratory, a member of the CALICE collaboration. The performances on testboard and in the detector environment have been measured. It allowed to conclude on the advantages and drawbacks of using SKIROC2 in the calorimeter. After that the focus has been made on the design of a new read-out chip based on SKIROC2. The main goal was to preserve the good performances of SKIROC2 while trying to correct the encountered issues. This new ASIC has been developped in a newly released technology available during the design phase. Therefore the design has been started from scratch. The final chip is composed of building blocks rather than a ready-to-use read-out chip. Three charge preamplifier designs have been tested, the general architecture of a read-out channel being largely inspired by SKIROC2.

Η ανίχνευση των δυναμικών δραστηριότητας συμβάλλει στη μείωση των δεδομένων προς αποστολή από ένα εμφυτεύσιμο σύστημα ασύρματης καταγραφής της νευρωνικής δραστηριότητας ενός ζώντα οργανισμού. Η παρούσα Mεταπτυχιακή Διπλωματική Εργασία έχει ως στόχο την σχεδίαση ενός ανιχνευτή δυναμικών δραστηριότητας σε νευρωνικές κυματομορφές ικανό να λειτουργεί σε περιβάλλον χαμηλής τάσης τροφοδοσίας για την επίτευξη μειωμένης κατανάλωσης ισχύος. Για το σκοπό αυτό, προτείνεται η σχεδίαση συστημάτων στο πεδίο του λογαρίθμου με τη χρήση MOS τρανζίστορ που είναι πολωμένα στην περιοχή υποκατωφλίου. Αρχικά, μελετώνται τα φυσικά χαρακτηριστικά των δυναμικών δραστηριότητας, δηλαδή το συχνοτικό τους περιεχόμενο και το σχήμα τους στο πεδίο του χρόνου. Επίσης, παρουσιάζεται ο μη-γραμμικός τελεστής ενέργειας και ο λόγος για τον οποίο αυτός καθίσταται σημαντικός στην επεξεργασία νευρωνικών σημάτων. Στη συνέχεια, παρουσιάζονται οι βασικές αρχές για τη σχεδίαση κυκλωμάτων στο πεδίο του λογαρίθμου. Ακόμα, κάνοντας χρήση των βασικών δομικών μονάδων του λογαριθμικού πεδίου, των μη-γραμμικών διαγωγών Ε Cells, υλοποιούνται τόσο οι συμπληρωματικοί τελεστές όσο και οι δομές επεξεργασίας σήματος που είναι απαραίτητες για την πραγματοποίηση του μη-γραμμικού τελεστή ενέργειας. Οι δομές αυτές είναι διαφοριστές και πολλαπλασιαστές τεσσάρων τεταρτημορίων τρόπου ρεύματος. Τέλος, δίνεται η ολοκλήρωση του συστήματος με την σχεδίαση ενός συγκριτή ρεύματος που επιτελεί την λειτουργία της κατωφλιοποίησης. Για την εξομοίωση του συστήματος, χρησιμοποιείται μια νευρωνική κυματομορφή, το Analog Design Environment του λογισμικού Cadence και οι παράμετροι της τεχνολογίας TSMC 130nm. / The detection of action potentials contributes to the reduction of data to be transmitted by an implantable wireless neural activity recording system. The goal of the present M.Sc. Τhesis is the design of an action potential detector capable of operating in a low-voltage environment, in order to achieve reduced power dissipation. For this purpose, the log-domain designing technique is suggested by using MOS transistors operating in the subthreshold region. Initially, the physical characteristics of action potentials are studied, i.e. the frequential content and time-domain shape. Moreover, the nonlinear energy operator is presented in addition to the reason that makes this system crucial for neural signal processing. Thereafter, the basic principles of designing log-domain circuits are presented. Furthermore, the complementary operators as well as the signal processing blocks that are necessary for the realization of NEO are implemented by using the main log-domain building units, the nonlinear transconductors E cells. The blocks required for the NEO implementation are current-mode differentiators and four-quadrant multipliers. Finally, the complete system is given after the design of a current comparator which is responsible for the operation of thresholding. The simulation of the system has been performed through the utilization of the Analog Design Environment of Cadence software and the design kit of TSMC 130nm process in addition to a neural waveform.

Sparse approximation is a Bayesian inference program with a wide number of signal processing applications, such as Compressed Sensing recovery used in medical imaging. Previous sparse coding implementations relied on digital algorithms whose power consumption and performance scale poorly with problem size, rendering them unsuitable for portable applications, and a bottleneck in high speed applications. A novel analog architecture, implementing the Locally Competitive Algorithm (LCA), was designed and programmed onto a Field Programmable Analog Arrays (FPAAs), using floating gate transistors to set the analog parameters. A network of 6 coefficients was demonstrated to converge to similar values as a digital sparse approximation algorithm, but with better power and performance scaling. A rate encoded spiking algorithm was then developed, which was shown to converge to similar values as the LCA. A second novel architecture was designed and programmed on an FPAA implementing the spiking version of the LCA with integrate and fire neurons. A network of 18 neurons converged on similar values as a digital sparse approximation algorithm, with even better performance and power efficiency than the non-spiking network. Novel algorithms were created to increase floating gate programming speed by more than two orders of magnitude, and reduce programming error from device mismatch. A new FPAA chip was designed and tested which allowed for rapid interfacing and additional improvements in accuracy. Finally, a neuromorphic chip was designed, containing 400 integrate and fire neurons, and capable of converging on a sparse approximation solution in 10 microseconds, over 1000 times faster than the best digital solution.