Submitted by Filipe dos Santos (fsantos@pucsp.br) on 2017-12-11T11:12:22Z No. of bitstreams: 1 Fábio Mariano Borges.pdf: 24818396 bytes, checksum: 907b16881a5f0b26717b3573507ca0d4 (MD5) / Made available in DSpace on 2017-12-11T11:12:22Z (GMT). No. of bitstreams: 1 Fábio Mariano Borges.pdf: 24818396 bytes, checksum: 907b16881a5f0b26717b3573507ca0d4 (MD5) Previous issue date: 2017-10-31 / Digital activism or netativism is a recent advent and expression of the political exercise of users of the cyber world, especially of social networks. One of its types refers to the manifestations of the consumers against the companies through denunciations of crimes and attempt to promote boycott against them, in order to positive results for the collective. In this sense, consumption is seen as an area to political exercise, and this type of practice is even more democratized and accessible through social networks. The present study reflects about the reconfiguration of consumerism, very recently impacted by consumer netativism. Consumerism is a sociological term that names the set of consumer practices in order to exercise power, conquest, maintenance of rights and resistance to the commercial interests of the companies. The object of research is the manifestations of consumer indignation on Facebook between the years 2012 and 2017. For that, was conducted netnography, through monitoring the clashes between consumers and businesses on Facebook. In this sense, the study analyzes consumerism in the form of netativism, as a device of power, as well as consumption, both situated in the concept of biopolitics developed by Foucault / O ativismo digital ou netativismo é um advento recente e expressão do exercício político dos usuários do mundo cibernético, em especial das redes sociais. Uma de suas modalidades refere-se às manifestações dos consumidores contra as empresas através de denúncias de delitos e tentativa de promover boicote contra elas, a fim de resultados positivos para o coletivo. Nesse sentido, o consumo é visto como um terreno propício ao exercício político, sendo que esse tipo de prática é ainda mais democratizada e acessível através das redes sociais. O presente estudo trata sobre a reconfiguração do consumerismo, muito recentemente impactado pelo netativismo de consumidores. O consumerismo é um termo sociológio que nomea o conjunto de práticas de consumidores a fim do exercício de poder, conquista, manutenção de direitos e resistência frente aos interesses comerciais das empresas. O objeto de pesquisa aborda as manifestações de indignação dos consumidores no Facebook entre os anos de 2012 e 2017. Para tanto, foi realizada netnografia, através de acompanhamento e monitoramento dos embates no Facebook entre consumidores e empresas. Neste sentido, o estudo analisa o consumerismo sob a forma de netativismo e as relaçãoes de consumo, como dispositivos de poder, ambos situados no conceito de biopolítica desenvolvido por Foucault

A comunicação de Voz sobre IP (VoIP) vem aumentando com o decorrer do tempo e as redes de comunicação estão se tornando cada vez mais congestionadas, ocasionando perda de pacotes e latência nas redes, prejudicando diretamente a qualidade das comunicações de voz. Neste trabalho, foi estudado em detalhe como a qualidade do sinal de voz transmitido em uma comunicação VoIP é afetada por parâmetros da rede e pelo tipo de codificador utilizado na comunicação. Uma contribuição importante deste trabalho é a apresentação de uma metodologia que serve para predizer o comportamento de um codificador de voz em diferentes cenários de redes. O estabelecimento de um mecanismo de controle que otimize a utilização da rede e ao mesmo tempo garanta a melhor qualidade possível do sinal de voz transmitido vem sendo motivo de pesquisa. O emprego de codificadores multitaxa nas comunicações de voz possibilita a implementação de algoritmos que controlem a comutação destas taxas de codificação baseados em diferentes fatores de decisão como as características do sinal de voz a ser transmitido ou empregando a informação dos parâmetros de rede. Este trabalho apresenta um algoritmo de determinação de taxa de codificação com fator de decisão baseado na qualidade do sinal avaliada no ponto da recepção ou em algum ponto intermediário. Para realização dos testes montou-se um cenário de emulação de rede IP para o estabelecimento de uma chamada VoIP, onde são utilizados codificadores multitaxa (ITU-T G.726 e Speex). Para avaliação da qualidade do sinal de voz foi utilizada a recomendação ITU-T P.563, sendo que o índice MOS obtido no ponto de recepção é transmitido utilizando um laço de transmissão, que forma parte da estrutura do mecanismo de controle apresentado neste trabalho. Este laço de transmissão é implementado via socket sobre uma comunicação UDP. Como as ferramentas utilizadas são todas freeware, o cenário de emulação pode ser facilmente implementado por demais pesquisadores. Os resultados obtidos são confiáveis, já que para cenários onde se mesclam diferentes taxas de codificação, o índice MOS obtido é um valor que está na faixa dos valores obtidos nos cenários onde se utilizou taxa de codificação única. O correto desempenho do mecanismo do RDA também foi verificado, sendo que a qualidade do sinal de voz decresce, o mecanismo de controle no RDA comuta a uma taxa de codificação menor, garantindo o melhor uso do canal de transmissão. Quando os parâmetros da rede passam a melhores condições, o índice MOS do sinal aumenta e o RDA comuta a uma taxa de codificação maior obtendo uma qualidade mais alta na comunicação. / Voice over IP (VoIP) communications are becoming increasingly popular so that data communication networks are ever more prone to degradations like packet losses and rising latency. In this work, it was studied in detail how the quality of the speech signal transmitted in a VoIP communication is affected by parameters of the network and the type of codec used in the communication. An important contribution of this work is to predict the behavior of a speech codec in different network scenarios. The main goal of this research has been the development of an algorithm that constrains rate allocation to a speech communication for best quality according to current network resource availability. The use of multirate codecs in speech communications makes it possible to implement control algorithms for coding rate switching. They are based on speech signal features or network trafic parameters. This work presents an algorithm for the determination of coding rate with decision factor based on speech quality evaluated at the point of reception or intermediate points. For accomplishment of the tests, a scenario of emulation of an IP network for the establishment of a VoIP call was built, where multi-rate codecs are used (ITU-T G.726 and Speex). For evaluation of the quality of the speech signal the Recommendation ITU-T P.563 was used, where the MOS index obtained in the reception is transmitted using a transmission loop, as a part in the control mechanism in the proposed algorithm. This transmission loop consists of a UDP message sent on a socket. As the tools used are all freeware, the simulation scenarios can easily be implemented by other researchers. The results are trustworthy, because for multirate scenarios, the MOS index obtained is a value that is between the ones obtained in the single-rate scenarios. The correct performance of the mechanism of the RDA was also verified, so that when the quality of the signal decreases, the control mechanism in the RDA switches to a lower coding rate, ensuring the best use of the transmission canal. When the parameters of the network drive to best conditions, the MOS index of the signal increases and the RDA decides to switch to a higher coding rate achieving a higher communication quality.

Ubiquitous connectivity plays an important role in improving the quality of life in terms of economic development, health and well being, social justice and equity, as well as in providing new educational opportunities. However, rural communities which account for 46% of the world's population lacks access to proper connectivity to avail such societal benefits, creating a huge "digital divide" between the urban and rural areas. A primary reason is that the Information and Communication Technologies (ICT) providers have less incentives to invest in rural areas due to lack of promising revenue returns. Existing research and industrial attempts in providing connectivity to rural communities suffer from severe drawbacks, such as expensive wireless spectrum licenses and infrastructures, under- and over-provisioning of spectrum resources while handling heterogeneous traffic, lack of novel wireless technologies tailored to the unique challenges and requirements of rural communities (e.g., agricultural fields). Leveraging the recent advances in Dynamic Spectrum Access (DSA) technologies like wide band spectrum analyzers and spectrum access systems, and multi-radio access technologies (multi-RAT), this dissertation proposes a novel Diverse Band-aware DSA (d-DSA) network architecture, that addresses the drawbacks of existing standard and DSA wireless solutions, and extends ubiquitous connectivity to rural communities; a step forward in the direction of the societal and economic improvements in rural communities, and hence, narrowing the "digital divide" between the rural and urban societies. According to this paradigm, a certain wireless device is equipped with software defined radios (SDRs) that are capable of accessing multiple (un)licensed spectrum bands, such as, TV, LTE, GSM, CBRS, ISM, and possibly futuristic mmWaves. In order to fully exploit the potential of the d-DSA paradigm, while meeting heterogeneous traffic demands that may be generated in rural communities, we design efficient routing strategies and optimization techniques, which are based on a variety of tools such as graph modeling, integer linear programming, dynamic programming, and heuristic design. Our results on realistic traces in a large variety of rural scenarios show that the proposed techniques are able to meet the heterogeneous traffic requirements of rural applications, while ensuring energy efficiency and robustness of the architecture for providing connectivity to rural communities.

The growing computational demand of scientific applications has greatly motivated the development of large-scale high-performance computing (HPC) systems in the past decade. To accommodate the increasing demand of applications, HPC systems have been going through dramatic architectural changes (e.g., introduction of many-core and multi-core systems, rapid growth of complex interconnection network for efficient communication between thousands of nodes), as well as significant increase in size (e.g., modern supercomputers consist of hundreds of thousands of nodes). With such changes in architecture and size, the energy consumption by these systems has increased significantly. With the advent of exascale supercomputers in the next few years, power consumption of the HPC systems will surely increase; some systems may even consume hundreds of megawatts of electricity. Demand response programs are designed to help the energy service providers to stabilize the power system by reducing the energy consumption of participating systems during the time periods of high demand power usage or temporary shortage in power supply. This dissertation focuses on developing energy-efficient demand-response models and algorithms to enable HPC system's demand response participation. In the first part, we present interconnection network models for performance prediction of large-scale HPC applications. They are based on interconnected topologies widely used in HPC systems: dragonfly, torus, and fat-tree. Our interconnect models are fully integrated with an implementation of message-passing interface (MPI) that can mimic most of its functions with packet-level accuracy. Extensive experiments show that our integrated models provide good accuracy for predicting the network behavior, while at the same time allowing for good parallel scaling performance. In the second part, we present an energy-efficient demand-response model to reduce HPC systems' energy consumption during demand response periods. We propose HPC job scheduling and resource provisioning schemes to enable HPC system's emergency demand response participation. In the final part, we propose an economic demand-response model to allow both HPC operator and HPC users to jointly reduce HPC system's energy cost. Our proposed model allows the participation of HPC systems in economic demand-response programs through a contract-based rewarding scheme that can incentivize HPC users to participate in demand response.

Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this thesis, the design, implementation and evaluation of on-line modules and networks for DSP applications, using FPGAS as the target technology, are shown. The presented designs of the modules are highly optimized for the target hardware, which allows a significant increase in efficiency compared to standard on-line designs. The design process for the networks of on-line modules is described in detail, and a methodology to analyze the dataflow and timing is presented. A comparison of on-line signal processing solutions with other approaches. that are available as IP building blocks or components, is given. It is shown that on-line designs are better in terms of latency but that they can not compete in terms of throughput and area for basic applications like FIR filters. However, it is also shown that on-line designs are able to overtake other approaches as the applications become more sophisticated. e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches, such as serial distributed arithmetic. For these applications, online arithmetic shows, compared to other designs, a lower latency and a significant area reduction, while maintaining a high throughput. Several properties of algorithms for which on-line arithmetic is advantageous are identified in this thesis. With this information, it is possible to determine if an on-line solution for an application should be considered. The conclusions are based on experimental data collected using CAD tools for the Xilinx XC4000 family of chips. All the designs are synthesized for the same type of devices for comparison, avoiding rough estimates of the system performance. This generates a more reliable comparison allowing designers to decide between on-line or conventional approaches for their DSP designs. / Graduation date: 2002

This thesis deals with the synchronization of digital communication systems. Synchronization (from the Greek syn (together) and chronos (time)) denotes the task of making two systems running at the same time. In communication systems, the synchronization of the transmitter and the receiver requires to accurately estimate a number of parameters such as the carrier frequency and phase offsets, the timing epoch... In the early days of digital communications, synchronizers used to operate in either data-aided (DA) or non-data-aided (NDA) modes. However, with the recent advent of powerful coding techniques, these conventional synchronization modes have been shown to be unable to properly synchronize state-of-the-art receivers. In this context, we investigate in this thesis a new family of synchronizers referred to as code-aided (CA) synchronizers. The idea behind CA synchronization is to take benefit from the structure of the code used to protect the data to improve the estimation quality achieved by the synchronizers. In a first part of the thesis, we address the issue of turbo synchronization, i.e., the iterative synchronization of continuous parameters. In particular, we derive several mathematical frameworks enabling a systematic derivation of turbo synchronizers and a deeper understanding of their behavior. In a second part, we focus on the so-called CA hypothesis testing problem. More particularly, we derive optimal solutions to deal with this problem and propose efficient implementations of the proposed algorithms. Finally, in a last part of this thesis, we derive theoretical lower bounds on the performance of turbo synchronizers.

Cyber attacks against companies and organizations can result in high impact losses that include damaged credibility, exposed vulnerability, and financial losses. Until the 21st century, insiders were often overlooked as suspects for these attacks. The 2010 CERT Cyber Security Watch Survey attributes 26 percent of cyber crimes to insiders. Numerous real insider attack scenarios suggest that during, or directly before the attack, the insider begins to behave abnormally. We introduce a method to detect abnormal behavior by profiling users. We utilize the k-means and kernel density estimation algorithms to learn a user’s normal behavior and establish normal user profiles based on behavioral data. We then compare user behavior against the normal profiles to identify abnormal patterns of behavior.

Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates based on a decision-directed device. Timing recovery performance is a strong function of the reliability of decisions, and hence, of the channel signal-to-noise ratio (SNR). Iteratively decodable error-control codes (ECCs) like turbo codes and LDPC codes allow operation at SNRs lower than ever before, thus exacerbating timing recovery. We propose iterative timing recovery, where the timing recovery block, the equalizer and the ECC decoder exchange information, giving the timing recovery block access to decisions that are much more reliable than the instantaneous ones. This provides significant SNR gains at a marginal complexity penalty over a conventional turbo equalizer where the equalizer and the ECC decoder exchange information. We also derive the Cramer-Rao bound, which is a lower bound on the estimation error variance of any timing estimator, and propose timing recovery methods that outperform the conventional PLL and achieve the Cramer-Rao bound in some cases. At low SNR, timing recovery suffers from cycle slips, where the receiver drops or adds one or more symbols, and consequently, almost always the ECC decoder fails to decode. Iterative timing recovery has the ability to corrects cycle slips. To reduce the number of iterations, we propose cycle slip detection and correction methods. With iterative timing recovery, the PLL with cycle slip detection and correction recovers most of the SNR loss of the conventional receiver that separates timing recovery and turbo equalization.

This thesis presents methods for developing FPGA-based test solutions that solve the challenges of evaluating source-synchronous and protocol-laden systems and devices at multi-gigabit per second signaling rates. These interfaces are becoming more prevalent in emerging designs and are difficult to test using traditional automated test equipment (ATE) and test instrumentation which were designed for testing designs utilizing synchronous and deterministic signaling. The main motivation of this research was to develop solutions that address these challenges. The methods shown in this thesis are used to design a test architecture consisting of custom hardware components, reprogrammable digital logic for hardware integration, and a software interface for external data transport and configuration. The hardware components consist of a multi-GHz field programmable gate array (FPGA) based interface board providing processing, control, and data capabilities to the system and enhanced by one or more application modules which can be tailored for specific test functionality compatible with source-synchronous and protocol interfaces. Software controls from a host computer provide high and low level access to the internal tester data and configuration memory space. The architecture described in this thesis is demonstrated through a specific test solution for a high-speed optical packet switched network called the Data Vortex. Reprogrammable firmware and software controls allow for a high degree of adaptability and application options. The modularized implementation of the hardware elements introduces additional adaptability and future upgradability, capable of incorporating new materials and design techniques for the test platform and application modules.

Cyber attacks against companies and organizations can result in high impact losses that include damaged credibility, exposed vulnerability, and financial losses. Until the 21st century, insiders were often overlooked as suspects for these attacks. The 2010 CERT Cyber Security Watch Survey attributes 26 percent of cyber crimes to insiders. Numerous real insider attack scenarios suggest that during, or directly before the attack, the insider begins to behave abnormally. We introduce a method to detect abnormal behavior by profiling users. We utilize the k-means and kernel density estimation algorithms to learn a user’s normal behavior and establish normal user profiles based on behavioral data. We then compare user behavior against the normal profiles to identify abnormal patterns of behavior.