A vida de milhões de pessoas é afetada por problemas de deficiência auditiva, incapacitando-as de ouvirem os sons naturalmente. O uso de aparelhos de auxílio auditivo minimiza o efeito das deficiências, pois possibilita tratamento dos sinais auditivos através de sofisticados algoritmos que eliminam ruídos e amplificam os sinais de interesse. Este trabalho propõem a especificação de um sistema integrado, otimizado em termos de consumo de potência, para realizar o processamento de sinais digitais em aparelhos de auxílio auditivo digital. Foram desenvolvidos dois blocos para processamento hardwired, que substituem o processamento realizado por software, cuja finalidade é filtrar os sinais sonoros digitalizados com menor consumo. Um dos blocos, um filtro FIR de até 128 coeficientes, pode ser utilizado como filtro do tipo passa baixa ou passa altas frequências. O outro bloco, para executar o algoritmo ALE, é utilizado para eliminar ruídos periódicos. Os blocos desenvolvidos e implementados foram compilados e simulados para comprovar a funcionalidade. Os resultados das simulações mostraram que eles atendem as especificações de funcionalidade. Os blocos foram também sintetizados em uma tecnologia CMOS de 0,35 &#956m, três níveis de metal, para assim se ter as estimativas de área do circuito e de consumo de potência. A área do layout final foi de 14 mm². O consumo de potência estimado é de 0,30 mW para frequência de clock de 300 kHz (o que permite que um filtro FIR processe uma amostra a cada 240 &#956s, no pior caso, e o ALE, uma a cada 36 &#956s), e de 5,06 mW para frequência de clock de 5,0 MHz (filtro FIR processa uma amostra a cada 14,4 &#956s e o ALE, uma a cada 2,2 &#956s). As estimativas de consumo foram feitas considerando os dois blocos operando simultaneamente e com tensão de alimentação de 1,8 V. Para todo o sistema integrado proposto, obtive-se, com um cenário específico, o consumo de potência de 1,1 mW, considerando dois Filtros Configuráveis, um Filtro ALE e um DSP. / The live of millions of people are affected by hearing problems, disabling them from hearing the sounds naturally. The use of hearing aids devices minimizes the effect of deficiencies, since it allows processing of auditory signals through sophisticated algorithms that eliminate noise and amplify the signals of interest. This work proposes the specification of an integrated system, optimized in terms of power consumption, to perform digital signal processing in digital hearing aid devices. Were developed two blocks of hardwired processing, replacing software processing, whose purposes are to filter the digitized audio signals with lower consumption. One of the blocks, an FIR filter up to 128 coefficients can be used as a low pass or high pass filter. The other block, to run the ALE algorithm, is used to eliminate periodic noises. The blocks developed and implemented were compiled and simulated to demonstrate their functionality. The simulation results show that they meet the specifications of functionality. The blocks were also synthesized in a 0.35 &#956m CMOS technolog, three metal levels, in order to have estimatives of circuit area and power consumption. The area of the final layout was 14,0 mm². The estimated power consumption is 0.30 mW for clock frequency of 300 kHz (which allows a FIR filter to process one sample every 240 &#956s in the worst case, and ALE, one every 36 &#956s), and 5.06 mW for clock frequency of 5.0 MHz (FIR filter processing one sample every 14.4 &#956s, and ALE, one every 2.2 &#956s). Consumption estimates were made considering the two blocks operating simultaneously and supply voltage of 1.8 V. For all the proposed integrated system, it was found, for a specific scenario, the power consumption of 1.1 mW, considering two configurable filters, one filter ALE and one DSP.

A vida de milhões de pessoas é afetada por problemas de deficiência auditiva, incapacitando-as de ouvirem os sons naturalmente. O uso de aparelhos de auxílio auditivo minimiza o efeito das deficiências, pois possibilita tratamento dos sinais auditivos através de sofisticados algoritmos que eliminam ruídos e amplificam os sinais de interesse. Este trabalho propõem a especificação de um sistema integrado, otimizado em termos de consumo de potência, para realizar o processamento de sinais digitais em aparelhos de auxílio auditivo digital. Foram desenvolvidos dois blocos para processamento hardwired, que substituem o processamento realizado por software, cuja finalidade é filtrar os sinais sonoros digitalizados com menor consumo. Um dos blocos, um filtro FIR de até 128 coeficientes, pode ser utilizado como filtro do tipo passa baixa ou passa altas frequências. O outro bloco, para executar o algoritmo ALE, é utilizado para eliminar ruídos periódicos. Os blocos desenvolvidos e implementados foram compilados e simulados para comprovar a funcionalidade. Os resultados das simulações mostraram que eles atendem as especificações de funcionalidade. Os blocos foram também sintetizados em uma tecnologia CMOS de 0,35 &#956m, três níveis de metal, para assim se ter as estimativas de área do circuito e de consumo de potência. A área do layout final foi de 14 mm². O consumo de potência estimado é de 0,30 mW para frequência de clock de 300 kHz (o que permite que um filtro FIR processe uma amostra a cada 240 &#956s, no pior caso, e o ALE, uma a cada 36 &#956s), e de 5,06 mW para frequência de clock de 5,0 MHz (filtro FIR processa uma amostra a cada 14,4 &#956s e o ALE, uma a cada 2,2 &#956s). As estimativas de consumo foram feitas considerando os dois blocos operando simultaneamente e com tensão de alimentação de 1,8 V. Para todo o sistema integrado proposto, obtive-se, com um cenário específico, o consumo de potência de 1,1 mW, considerando dois Filtros Configuráveis, um Filtro ALE e um DSP. / The live of millions of people are affected by hearing problems, disabling them from hearing the sounds naturally. The use of hearing aids devices minimizes the effect of deficiencies, since it allows processing of auditory signals through sophisticated algorithms that eliminate noise and amplify the signals of interest. This work proposes the specification of an integrated system, optimized in terms of power consumption, to perform digital signal processing in digital hearing aid devices. Were developed two blocks of hardwired processing, replacing software processing, whose purposes are to filter the digitized audio signals with lower consumption. One of the blocks, an FIR filter up to 128 coefficients can be used as a low pass or high pass filter. The other block, to run the ALE algorithm, is used to eliminate periodic noises. The blocks developed and implemented were compiled and simulated to demonstrate their functionality. The simulation results show that they meet the specifications of functionality. The blocks were also synthesized in a 0.35 &#956m CMOS technolog, three metal levels, in order to have estimatives of circuit area and power consumption. The area of the final layout was 14,0 mm². The estimated power consumption is 0.30 mW for clock frequency of 300 kHz (which allows a FIR filter to process one sample every 240 &#956s in the worst case, and ALE, one every 36 &#956s), and 5.06 mW for clock frequency of 5.0 MHz (FIR filter processing one sample every 14.4 &#956s, and ALE, one every 2.2 &#956s). Consumption estimates were made considering the two blocks operating simultaneously and supply voltage of 1.8 V. For all the proposed integrated system, it was found, for a specific scenario, the power consumption of 1.1 mW, considering two configurable filters, one filter ALE and one DSP.

[pt] A indústria eletrônica tem apresentado uma demanda crescente pela fabricação de aparelhos onde o baixo consumo de energia é uma das características mais importantes. Como exemplo, temos os telefones celulares, os computadores pessoais portáteis e os implantes biomédicos. Este trabalho investiga o projeto e o layout de células analógicas de consumo mil vezes menos (micropower) que os circuitos convencionais. As células desenvolvidas tanto podem ser usadas em aplicações analógicas quanto em circuitos híbridos formados por blocos digitais e blocos analógicos em um mesmo circuito integrado (mixed-mode). O trabalho desenvolvido envolveu 7 etapas principais: o estudo da operação do transistor MOS polarizado na região de inversão fraca comparado com a região de inversão forte; o estudo de estruturas básicas com dois transitores operando na inversão fraca; a conversão dos parâmetros de fabricante para a simulação das células; estudo de células analógicas a e seu projeto para baixo consumo; simulação das células e comparação com células comerciais; estudo da variação dos parâmetros de fabricação; estudo de técnicas de layout para células analógicas. Inicialmente o trabalho apresenta um resumo do estado da arte em projetos de circuitos integrados analógicos CMOS e, introduz o conceito da operação do transistor MOS em inversão fraca (weak inversion). O estudo de estruturas básicas, tais como espelhos de corrente, é o passo seguinte para a compreensão das limitações da operação dos transistores na fraca inversão e a análise de suas vantagens e desvantagens. A conversão dos parâmetros de processos fornecido pelo fabricante, do SPICE nível 2 para o SMASH nível 5, é um passo importante para uma simulação mais fiel do transistor real operando na região de inversão fraca, usando o novo modelo EKV (desenvolvido pela Escola Politécnica Federal de Lausanne - EPFL). O desenvolvimento dos blocos funcionais analógicas, tais como amplificadores operacionais, tece como estratégia de trabalho partir de especificações de células existentes em bibliotecas de fabricantes comerciais com tecnologia reconhecida sobre o assunto, e tentar reproduzir as suas características através do projeto de células dedicadas. Foram avaliadas algumas topologias de uma mesma célula com o objetivo de realizar a comparação entre elas. As medidas de desempenho das células para a comparação com as comerciais, foram realizadas com o uso de arquivos hierárquicos de simulação, visando a redução da quantidade de arquivos. Foi realizado um estudo de como a variação do processo de fabricação pode afetar o desempenho das células projetadas por análise de Montecarlo. São mostradas técnicas de layout de células analógicas que visam reduzir o descasamento entre transistores, faro este que poderia levar o circuito a apresentar comportamento diferente daquele especificado inicialmente. Os resultados alcançados demonstraram ser possível o desenvolvimento de células analógicas de baixo consumo. Através do uso da técnica de operação do transistor na região de inversão fraca, obteve-se desempenho comparável aos circuitos comerciais, tornando possível a criação de uma biblioteca de células analógicas mais ampla sem a necessidade da dependência do know-how dos fabricantes comerciais. / [en] Low power supply consumption hás become one of the main issue in eletronic industry for many product áreas such as cellular telephones, portable personal computers and biomedical implants. The aim of this work is to investigate the main drawbacks involved in the design of CMOS analog cells biased in weak inversion. Biasing a cell in weak inversion makes it possible to archieve a power consumption that is one thousandth lower than common analog cells designed to operate in strong inversion. This work has involved the following subject: a study of models for MOS transistors operating in weak inversion and strong inversion regions; a methodology to convert LEVEL 2 Spice model to EKV model; study of basic analog cell blocks suitable to low power mixed mode IC design; design methodology for low power analog cells; comparison between these cells and some commercial ones; study of analog layout techniques. Firstly, this work reviews the state-of-art of analog cell design including MOS transistor operation and modeling in the weak inversion region. Secondly we discuss the operation of some basic structures, such as current mirors and differential amplifiers, biased in weak inversion. This study helped us to understand the benefits and drawbacks involved in working with MOS transistors biased in this region. Next we describe a methodology to convert process parameters suppied by the foundries, usually LEVEL 2 Spice model, to the EKV model that was developed by EPFL (Swiss Federal Institute of Technology - Lausanne). Since EKV model is continuous in all regions, we expect to archieve better agreement between simulation results and manufacturing results. In order to test and validate the design methodology we chose to develop first a set of cells for this foundry comforming to a foundry with expertise in low voltage analog cell design. These tests were carried ou through standardized hierarchical simulation files in order to decrease the total number of simulatiom files required. Finally, we present some techniques for the layout of analog cells that improve circuit sensibility to transistor mismatching and process variation. The work shows us that it is feasible to design low power analog circuit using MOS transistors operating in weak inversion region. The methodology was even able to synthesize cells that are similar in performance to commercial ones. Therefore, it is possible to develop a çow power analog cell library which is suitable to designing application specific integrated circuits.

Ce travail porte sur l'étude de faisabilité d'une architecture radio, dédiée aux applications WPANs nomades et faible consommation en utilisant la bande autour de 60 GHz. Des débits de l'ordre de Gbps, une compacité élevée et une consommation de puissance faible sont obtenus en réalisant une conception conjointe front-end antenne. Avant de proposer l'architecture adaptée au cahier de charge, une étude préalable du canal de propagation à 60 GHz est faite. Les deux principales normes de canal IEEE, le 802.15.3c et le 802.11.ad, sont étudiées. L'analyse d'une architecture impulsionnelle mono-bande adaptée aux systèmes à faible consommation montre une limitation du débit quand des antennes non directives sont utilisées dans la norme de canal 802.11.ad. Afin de remédier à ce problème, une architecture multi-bande impulsionnelle MBOOK à récepteur non-cohérent est proposée. Cette architecture autorise un haut débit avec l'utilisation de quatre sous bandes. Elle conduit également à une consommation faible grâce à l'utilisation d'un récepteur non-cohérent et d'une topologie différentielle de l'émetteur évitant l'intégration de combineurs. Pour valider le concept d'architecture proposée, des antennes différentielles dédiées à l'architecture différentielle sont conçues. Les premières antennes sont de type patch différentiel excité par des lignes microrubans. Ces dernières présentent des caractéristiques de rayonnement adaptées aux besoins du cahier de charge. Néanmoins elles occupent une surface importante. Afin d'avoir une meilleure compacité, un patch alimenté par couplage à fente est développé. Il exploite deux polarisations linéaires orthogonales excitées par une paire d'entrées différentielles. Afin d'obtenir la directivité élevée nécessaire pour les scénarios LOS à 60 GHz sans utiliser de réseaux d'antennes ou de lentilles diélectriques, des métamatériaux sont utilisés. La mesure des antennes est basée sur la réalisation d'une transition guide d'onde WR-15 ligne microruban pour connecter l'antenne à l'analyseur de réseau. La mesure de l'antenne patch différentielle présente une bonne concordance avec les résultats de simulations. La technologie TQP15 de TriQuint est utilisée pour concevoir les différents éléments de la partie front-end. L'évaluation de la consommation globale d'émetteur valide l'architecture proposée en termes de faible consommation. Ce travail se termine par une évaluation du débit du système en tenant en compte de l'influence de l'antenne et du canal de propagation. Cette évaluation prouve la potentialité de l'architecture en termes de haut débit. On propose finalement une technique basée sur la technologie LTCC pour l'assemblage antenne/front-end / This work deals with the feasibility study of a radio architecture dedicated to mobile WPAN applications at 60 GHz and characterized by a low power consumption. Data rates of the order of Gbps, high compactness and low power consumption are obtained by co-designing the antenna and the front-end. Before proposing the architecture matching the specification needs, a preliminary study of the propagation channel at 60 GHz is made. The two main standards IEEE 802.15.3c and 802.11.ad the channel are studied. The analysis of a single-band architecture suitable for low-power systems shows a data rate limitation when directional antennas are used in the standard channel 802.11.ad. To address this problem, a multi-band impulse architecture MBOOK using a non-coherent receiver is proposed. This architecture allows high throughput with the use of four sub-bands. It also leads to a low power consumption through the use of a non-coherent receiver and a differential transmitter topology avoiding combiners. To validate the concept of the proposed architecture, differential antennas dedicated to the differential architecture are designed. Patch antennas excited by differential microstrip lines fulfil the needs of the specifications but occupy a large area. In order to miniaturize the antenna, slot-fed patch antennas are designed using two orthogonal linear polarizations excited by a pair of differential inputs. To achieve the high directivity required in LOS scenarios without using antenna arrays or dielectric lenses, metamaterials are used. The antenna measurement is based on the realization of a WR-15 waveguide-to-microstrip line transition to connect the antenna to the network analyzer. The differential measurement of the antenna patch exhibits a good agreement with the simulated results. The TriQuint's TQP15 technology is used to design the various circuits of the front-end. The emitter architecture is validated once the overall consumption has been evaluated. This work ends with an evaluation of the throughput of the system taking into account the influence of the antenna and the propagation channel. This evaluation shows the potential of the architecture in terms of high throughput. We finally propose an approach based on the LTCC technology for the antenna / front-end assembly

Στην παρούσα διπλωματική εργασία εκπονείται μελέτη που αφορά την σχεδίαση αναλογικών ηλεκτρονικών κυκλωμάτων για βιοϊατρικές εφαρμογές. Δίνεται μεγαλύτερη βαρύτητα στην υλοποίηση διαγωγών χαμηλής τροφοδοσίας και ενισχυτών ρεύματος οδηγούμενων από το υπόστρωμα. Όπως σε όλα τα διαφορικά κυκλώματα, έτσι και στους διαφορικούς διαγωγούς κύριο μέλημα των σχεδιαστών είναι η γραμμικότητα τους και οι παράμετροι που την επηρεάζουν. Προτείνεται ένας διαγωγός χαμηλής τροφοδοσίας που βασίζεται στην βαθμίδα ακόλουθου τάσης με αναστροφή και προσομοιώνεται για να μελετηθεί το εύρος της γραμμικότητας του, η απόκριση συχνότητας και η συμπεριφορά του σε χρονικά μεταβαλλόμενο ημιτονοειδές σήμα. Ο ενισχυτής ρεύματος οδηγούμενος από το υπόστρωμα που παρουσιάζεται σε αυτήν την εργασία εκμεταλλεύεται όλους τους βαθμούς ελευθερίας ενός MOS τρανζίστορ πολωμένου στην ασθενή αναστροφή και στον κόρο. Η τεχνική οδήγησης από το υπόστρωμα χρησιμοποιείται ευρέως στην σχεδίαση κυκλωμάτων χαμηλής τροφοδοσίας, αφού έχει μειωμένες απαιτήσεις τάσης, ενώ είναι και ανεξάρτητη από περιορισμούς σχετικούς με την τάση κατωφλίου. Επιπρόσθετα, τα τρανζίστορ με οδήγηση από το υπόστρωμα διατηρούνται στην περιοχή κόρου για αρνητικές, μηδενικές και σχετικά μικρές θετικές τιμές της τάσης πόλωσης VBS. Έτσι, μπορούν να επεξεργάζονται σήματα εισόδου κοινού τρόπου (common-mode input range) μεγάλης τιμής και με μεγάλο εύρος κυμάτωσης κάτι που δεν θα μπορούσε να επιτευχθεί με συμβατικές κυκλωματικές τεχνικές σε τόσο χαμηλή τάση τροφοδοσίας. Όμως, τα τρανζίστορ με οδήγηση από το υπόστρωμα έχουν μικρή τιμή διαγωγιμότητας και είναι ευαίσθητα στον θόρυβο. Άλλο μειονέκτημα της τεχνικής με οδήγηση από το υπόστρωμα είναι ότι η πόλωση των τρανζίστορ εξαρτάται από την τεχνολογία ολοκλήρωσης. Το κέρδος του ενισχυτή ρεύματος οδηγούμενου από το υπόστρωμα μεταβάλλεται με εκθετικό τρόπο. Αυτή η ιδιότητα είναι σημαντική και χρησιμοποιείται ευρέως σε συστήματα αυτομάτου ελέγχου κέρδους όπου το σήμα εισόδου μεταβάλλεται αρκετές τάξεις μεγέθους. Σε ένα παρόμοιο σύστημα χρησιμοποιούμε και τα προαναφερθέντα κυκλώματα και εξετάζουμε την συνολική συμπεριφορά του. Οι προδιαγραφές αυτών των κυκλωμάτων επιτρέπουν την εφαρμογή τους στην βιοϊατρική, αφού εμφυτεύσιμα συστήματα, βίο-αισθητήρες και βοηθητικά ακοής επεξεργάζονται σήματα σχετικά χαμηλών συχνοτήτων με χαμηλή τάση τροφοδοσίας. / This diploma thesis forms a study on the design of analog circuits for biomedical applications. We focus on the realization of low voltage transconductors and Bulk-Driven current amplifiers. Like all the differential circuits, the designers’ main concern for a differential transconductor is its linearity and the parameters that affect it. We propose a low voltage transconductor based on Flipped Voltage Follower topology and we simulate it in order to study the range of the linearity, frequency response and its behavior in temporally varying sinusoidal signal. The Bulk-Driven current amplifier presented in this thesis takes advantage of all degrees of freedom of a MOS transistor biased in weak inversion and in saturation. The Bulk-Driven technique is widely used in the design of low voltage supply, because it has reduced demands on voltage and is independent of restrictions related to the threshold voltage. Moreover, Bulk-Driven transistors are maintained in saturation for negative, zero and even small positive values of the bias voltage VBS. Consequently, they can process large input common mode signals and signals with large swing voltage range, a property that could not be achieved with conventional circuit techniques at low power supply voltages. However, the transconductance of a Bulk –Driven transistor is smaller and is sensitive to noise. Another disadvantage of the Bulk-Driven technique is that the polarity of the transistor is process related. The gain of the Bulk-Driven current amplifier varies exponentially. This property is important and it is used widely in systems of automatic gain control where input signals can range several orders of magnitude. The specifications of these circuits allow their appliance in biomedicine, because implanted systems, biosensors and hearing aids process signals of relatively small frequencies with low voltage supply.

Pour faire face à la forte augmentation de la consommation en climatisation et la consommation électrique associée, il est nécessaire de développer des systèmes de rafraîchissement basse consommation de bâtiment. Ce travail propose un nouveau système de rafraîchissement qui se veut économe en énergie, peu coûteux et simple à installer. Il associe les techniques de dissipation de chaleur par évaporation, rayonnement vers le ciel et géothermie. Ce système est constitué d'un réservoir poreux installé en extérieur et d'un réservoir de stockage placé dans le vide sanitaire. Lorsque le bâtiment a besoin de rafraîchissement, une pompe puise de l'eau fraîche dans le stockage, la fait passer dans le plancher rafraîchissant pour absorber la chaleur excédentaire du bâtiment puis stocke l'eau dans le réservoir poreux placé à l'extérieur. Le réservoir poreux refroidit l'eau qu'il contient par évaporation, rayonnement vers le ciel puis se vide dans le stockage. Le réservoir de stockage installé dans le vide sanitaire se refroidit aussi en continu grâce au contact direct avec le sol. Les propriétés poreuses et la géométrie du réservoir poreux influent fortement sur ses performances de refroidissement. Une étude paramétrique menée avec un modèle numérique simulant les transferts hydriques et thermique permet de choisir un réservoir adéquat pour cette application. Un réservoir poreux donnant de bonnes performances (70 W/m2 de puissance évaporative) a été identifié. Le système de rafraîchissement a été installé et testé expérimentalement sur une maison à échelle réelle à Bordeaux. Mis en service durant l'été 2015, le système a fonctionné de façon autonome durant 44 jours. L'utilisation de ce système a permis de maintenir durant la période de test un très bon confort thermique à l'intérieur d'un bâtiment expérimental bien isolé, non ventilé, avec des apports solaires, tout en ayant une consommation électrique faible (le COP moyen du système est de 20.8). Un modèle numérique du système complet a été développé sous Modelica, calibré sur les mesures expérimentales puis couplé à un modèle de bâtiment. Les résultats de simulation montrent que l'installation de ce système améliore nettement le confort intérieur du bâtiment sur l'ensemble de l'été pour toutes les configurations testées (climat, gestion des voletsdots). Un système aux dimensions optimisées (avec un stockage de 2.2 m3 et un réservoir poreux de 0.215 m3), installé sur une maison individuelle type RT2012 de 100 m2 à Bordeaux, fonctionne avec un COP moyen de 24 et permet de maintenir un bon niveau de confort à l'intérieur du bâtiment tout l'été. / To face the dramatic increase of energy consumption due to air conditioning use in buildings, new low energy consumption systems need to be developed. This work proposes a new cooling system which aims to be energy efficient, cheap and easy to install. This system takes advantage of evaporation cooling, ground earth cooling and sky radiative cooling techniques. The two main components of this new system are a porous tank set outside and a storage tank set in the basement of the building. When the inside house temperature exceeds the comfort temperature, cool water passes from the storage tank through the cooling floor, removes heat from the building and is then send to the porous tank. The water contained in the porous tank is cooled down due to evaporation and radiative effects and then flows back to the storage. The storage tank installed in the basement enables further cooling of the water thanks to direct contact with the ground. Porous properties and geometry of the tank have a great influence on the cooling performances of the tank. A heat and mass transfer model has been developed to simulate the thermal and hydric behavior of the tank. This model has been used to choose an appropriate tank. A tank giving good performances (70 W/m2 of evaporative power) is identified. The complete cooling system has been installed on a house in Bordeaux and tested at real scale during an experimental campaign. The system worked for 44 days during summer 2015 and allowed to maintain a very good thermal comfort level in the experimental building (insulated, with solar load and without ventilation). Its very low electricity needs brings the average coefficient of performance of the system to 20.8. A numerical model of the system has been developed, calibrated with experimental data and coupled with a building model. Simulation results show that for all tested configurations (climate, shading…), the system clearly improves the thermal comfort in the building. Optimized sizing, keepinp reasonnable tank sizes (storage and evaporator volumes of 2.2 m3 and 0.215 m3 respectively), shows that this system works with an average COP of 24 and maintains a good comfort level in an individual house of 100 m2 located in Bordeaux.

Submitted by Caroline Periotto (carol@ufscar.br) on 2016-09-21T19:41:59Z No. of bitstreams: 1 DissLSB.pdf: 3925370 bytes, checksum: 7ddbdbe82689da0dc8671987f57082c9 (MD5) / Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-09-23T18:30:25Z (GMT) No. of bitstreams: 1 DissLSB.pdf: 3925370 bytes, checksum: 7ddbdbe82689da0dc8671987f57082c9 (MD5) / Approved for entry into archive by Marina Freitas (marinapf@ufscar.br) on 2016-09-23T18:30:32Z (GMT) No. of bitstreams: 1 DissLSB.pdf: 3925370 bytes, checksum: 7ddbdbe82689da0dc8671987f57082c9 (MD5) / Made available in DSpace on 2016-09-23T18:30:39Z (GMT). No. of bitstreams: 1 DissLSB.pdf: 3925370 bytes, checksum: 7ddbdbe82689da0dc8671987f57082c9 (MD5) Previous issue date: 2016-04-01 / Não recebi financiamento / This paper presents an analysis of the development of self-compacting concrete with low consumption of Portland cement, and evaluates some of its properties in fresh and hardened state ( mechanical properties ). The production of concrete with low consumption of Portland cement of the concept of providing more sustainable construction based on the concrete industry, as increased longevity of raw materials deposits, reducing CO2 emissions and energy consumption and lower cost transport. It provides various technical improvements such as lower heat of hydration, shrinkage and cracking. Based on packaging concepts and particle dispersion suitable choice of materials and the use of mineral fílers and admixtures, there was obtained concrete with low consumption of cement and high strength, with a relative consumption of binder materials less than 5 kg / m³ to produce 1 MPa compressive strength. This research is characterized as a theoretical-experimental model, which were researched packaging methods of aggregates and mineral additions, studied the interaction between superplasticizer and cementitious materials, seeking a considerable reduction in cement content in mixtures of self-compacting concrete. Therefore, we used the dosage methodology presented by Gomes (2002) and also have certain mechanical properties of concrete and it is concluded by the results, the use of a structural concrete self-compacting with Portland cement consumption can reduced. / Este trabalho apresenta uma análise sobre a elaboração de concretos autoadensáveis com baixo consumo de cimento Portland, e avalia algumas das suas propriedades no estado fresco e endurecido (propriedades mecânicas). A confecção de concretos com baixo consumo de cimento Portland parte do conceito de possibilitar maior sustentabilidade da indústria da construção civil baseada no concreto, como maior longevidade das jazidas de matérias-primas, redução da emissão de CO2 e no consumo de energia e menores custos de transportes. Proporciona diversas melhorias técnicas, como menor calor de hidratação, retração e fissuração. Fundamentado em conceitos de empacotamento e dispersão de partículas, escolha adequada dos materiais e uso de adições minerais e fíleres, obtiveram-se concretos com baixo consumo de cimento e alta resistência, com consumo relativo de materiais aglomerantes inferior a 5 kg/m³ para produzir 1 MPa de resistência à compressão. Esta pesquisa caracteriza-se como um modelo teórico-experimental, onde foram pesquisados métodos de empacotamento dos agregados e adições minerais, estudada a interação entre o aditivo superplastificante e os materiais cimentícios, buscando uma redução considerável do teor de cimento nas misturas de concretos autoadensáveis. Diante disso, utilizou-se a metodologia de dosagem apresentada por Gomes (2002) e também foram determinadas as propriedades mecânicas dos concretos e conclui-se, mediante aos resultados obtidos, que é possível o emprego de um concreto estrutural autoadensável com consumo de cimento Portland reduzido.

Dans cette thèse, une méthode de résolution de problèmes de commande optimale non linéaires sous contraintes d'état et de commande. Cette méthode repose sur l'adaptation des méthodes de points intérieurs, utilisées en optimisation de dimension finie, à la commande optimale. Un choix constructif de fonctions de pénalisation intérieure est fourni dans cette thèse. On montre que ce choix permet d'approcher la solution d'un problème de commande optimale sous contraintes en résolvant une suite de problèmes de commande optimale sans contraintes dont les solutions sont simplement caractérisées par les conditions de stationnarité du calcul des variations.Deux études dans le domaine de la gestion de l'énergie dans les bâtiments sont ensuite conduites. La première consiste à quantifier la durée maximale d'effacement quotidien du chauffage permettant de maintenir la température intérieure dans une certaine bande de confort, et ce pour différents types de bâtiments classés de mal à bien isolés. La seconde étude se concentre sur les bâtiments BBC et consiste à quantifier la capacité de ces bâtiments à réaliser des effacements électriques complets du chauffage de 6h00 à 22h00 tout en maintenant, là encore, la température intérieure dans une bande de confort. Cette étude est réalisée sur l'ensemble de la saison de chauffe. / This thesis exposes a methodology to solve constrained optimal controlof non linear systems by interior penalty methods. A constructivechoice for the penalty functions used to implement the interior methodis exhibited in this thesis. It is shown that itallows us to approach the solution of the non linear optimal controlproblem using a sequence of unconstrained problems, whose solutionsare readily characterized by the simple calculus of variations.Two representatives study of energy management in buildings are conducted using the provided algorithm. The first study consists in quantifying the maximal duration of daily complete load shiftings achievable by several buildings ranging from poorly to well insulated. The second study focuses on low consumption buildings and aim at quantifying the ability of these buildings to perform complete load shiftings of the heating electrical consumption from the day (6 a.m. to 10 p.m.) to the night period over the whole heating season.

Le rendement consommation/fréquence des futures générations de circuits intégrés sur silicium n’est pas satisfaisant à cause de la faible mobilité électronique de ce semi-conducteur et des relativement grandes tensions d’alimentation VDD requises. Ce travail se propose d’explorer numériquement les potentialités des transistors à effet de champ (FET) à base de matériaux III-V à faible bande interdite et à haute mobilité pour un fonctionnement en haute fréquence et une ultra basse consommation. Tout d’abord, l’étude consiste à analyser théoriquement le fonctionnement d’une capacité MOS III-V en résolvant de façon auto-cohérente les équations de Poisson et Schrödinger (PS). On peut ainsi comprendre comment et pourquoi les effets extrinsèques comme les états de pièges à l’interface high-k/III-V dégradent les caractéristiques intrinsèques. Pour une géométrie 2D, les performances des dispositifs sont estimées pour des applications logiques et analogiques à l’aide d’un modèle de transport quasi-balistique.Nous avons ensuite étudié plus en détails les performances des MOSFET III-V en régimes statiques et dynamiques sous faible VDD, à l’aide du simulateur particulaire MONACO de type Monte Carlo. Les caractéristiques de quatre topologies de MOSFET ont été quantitativement étudiées, en termes de transport quasi-balistique, de courants statiques aux états passants et bloqués, de rendement fréquence/consommation et de bruit. Nous en tirons des conclusions sur l’optimisation de ces dispositifs. Enfin, l'étude comparative avec un FET à base de Si démontre clairement le potentiel des MOSFET III-V pour les applications à haute fréquence, à faible puissance de consommation et à faible bruit. / The optimal frequency performance/power-consumption trade-off is very difficult to achieve using CMOS technology because of low Si carrier mobility and relatively large supply voltage (VDD) required for circuit operation. The main objective of this work is to theoretically explore, in terms of operation frequency and power consumption, the potentialities of nano-MOSFET based on III-V materials with low energy bandgap and high electron mobility.First, this work analyzes theoretically the operation of a III-V MOS capacitor using self-consistent solution of Poisson - Schrödinger system equation. We can thus understand how and why the interface trap state densities at high-k/III-V interfaces degrade the intrinsic characteristics. For a 2D geometry, the performance of devices is estimated for digital and analog applications using a model of quasi-ballistic transport.Then, we estimated the performance of III-V MOSFET in static and dynamic regimes under low VDD, using MONACO a Monte Carlo simulator. The characteristics of four designs of III-V MOSFET have been studied quantitatively in terms of quasi-ballistic transport, DC current in ON and OFF states, frequency/consumption efficiency and optimum matching conditions of noise. We provide the guideline on the design optimization of the devices.Finally, the comparative study with Si-based devices clearly demonstrates the potentiality of III-V nano-MOSFET architectures for high-frequency and low-noise application under low operating power and even for low voltage logic.

L'objectiu principal d'aquesta tesi consisteix a estudiar la factibilitat d'implementar un sensor càmera CNN amb plena funcionalitat basat en FPGA de baix cost adequat per a aplicacions en robots mòbils. L'estudi dels fonaments de les xarxes cel•lulars no lineals (CNNs) i la seva aplicació eficaç en matrius de portes programables (FPGAs) s'ha complementat, d'una banda amb el paral•lelisme que s'estableix entre arquitectura multi-nucli de les CNNs i els eixams de robots mòbils, i per l'altre banda amb la correlació dinàmica de CNNs i arquitectures memristive. A més, els memristors es consideren els substituts dels futurs dispositius de memòria flash per la seva capacitat d'integració d'alta densitat i el seu consum d'energia prop de zero. En el nostre cas, hem estat interessats en el desenvolupament d’FPGAs que han deixat de ser simples dispositius per a la creació ràpida de prototips ASIC per esdevenir complets dispositius reconfigurables amb integració de la memòria i els elements de processament general. En particular, s'han explorat com les arquitectures implementades CNN en FPGAs poden ser optimitzades en termes d’àrea ocupada en el dispositiu i el seu consum de potència. El nostre objectiu final ens ah portat a implementar de manera eficient una CNN-UM amb complet funcionament a un baix cost i baix consum sobre una FPGA amb tecnología flash. Per tant, futurs estudis sobre l’arquitectura eficient de la CNN sobre la FPGA i la interconnexió amb els robots comercials disponibles és un dels objectius d'aquesta tesi que se seguiran en les línies de futur exposades en aquest treball. / El objetivo principal de esta tesis consiste en estudiar la factibilidad de implementar un sensor cámara CNN con plena funcionalidad basado en FPGA de bajo coste adecuado para aplicaciones en robots móviles. El estudio de los fundamentos de las redes celulares no lineales (CNNs) y su aplicación eficaz en matrices de puertas programables (FPGAs) se ha complementado, por un lado con el paralelismo que se establece entre arquitectura multi -núcleo de las CNNs y los enjambres de robots móviles, y por el otro lado con la correlación dinámica de CNNs y arquitecturas memristive. Además, los memristors se consideran los sustitutos de los futuros dispositivos de memoria flash por su capacidad de integración de alta densidad y su consumo de energía cerca de cero. En nuestro caso, hemos estado interesados en el desarrollo de FPGAs que han dejado de ser simples dispositivos para la creación rápida de prototipos ASIC para convertirse en completos dispositivos reconfigurables con integración de la memoria y los elementos de procesamiento general. En particular, se han explorado como las arquitecturas implementadas CNN en FPGAs pueden ser optimizadas en términos de área ocupada en el dispositivo y su consumo de potencia. Nuestro objetivo final nos ah llevado a implementar de manera eficiente una CNN-UM con completo funcionamiento a un bajo coste y bajo consumo sobre una FPGA con tecnología flash. Por lo tanto, futuros estudios sobre la arquitectura eficiente de la CNN sobre la FPGA y la interconexión con los robots comerciales disponibles es uno de los objetivos de esta tesis que se seguirán en las líneas de futuro expuestas en este trabajo. / The main goal of this thesis consists in studying the feasibility to implement a full-functionality CNN camera sensor based on low-cost FPGA device suitable for mobile robotic applications. The study of Cellular Nonlinear Networks (CNNs) fundamentals and its efficient implementation on Field Programmable Gate Arrays (FPGAs) has been complemented, on one side with the parallelism established between multi-core CNN architecture and swarm of mobile robots, and on the other side with the dynamics correlation of CNNs and memristive architectures. Furthermore, memristors are considered the future substitutes of flash memory devices because of its capability of high density integration and its close to zero power consumption. In our case, we have been interested in the development of FPGAs that have ceased to be simple devices for ASIC fast prototyping to become complete reconfigurable devices embedding memory and processing elements. In particular, we have explored how the CNN architectures implemented on FPGAs can be optimized in terms of area occupied on the device or power consumption. Our final accomplishment has been implementing efficiently a fully functional reconfigurable CNN-UM on a low-cost low-power FPGA based on flash technology. Therefore, further studies on an efficient CNN architecture on FPGA and interfacing it with commercially-available robots is one of the objectives of this thesis that will be followed in the future directions exposed in this work.