The growing demand for UI test automation has triggered the development of many tools. Researchers and developers have been continuously working to further improvise the existing approaches. If we look at GUI test evolution we can observe a clear progress from manual testing towards complete automation. Numerous approaches have been made to automate the GUI testing process. Record and playback tools, key-word driven methodologies, event flow exploration strategies, model based approaches are continuously evolving with higher level of automation. Similarly, new ideas and strategies to make these tests efficient are also emerging. Optimization of this resource consuming activity is another very important aspect in this area.  Dependencies between different tests can create deadlock scenarios, while running larger test suites. A concept of Ordered Test Suite can be used to cope with such dependencies. Following the Model Driven Architecture initiative by Object Management Group, a new global trend of Model Driven Engineering is creating a big sensation in the field of model based software development. Using the same principle, studies have also been made to automatically generate tests from models. Behavioral models can be made using the model driven approaches and these models can be analyzed to generate tests automatically. This master thesis addresses different approaches made for Graphical User Interface test automation, some optimization issues and solutions, a case study done at a software company to automate User Interface testing and a model driven approach for automatic test case generation.

We tackle the problem of automated code generation for a High Level Architecture (HLA)- compliant federate application, given a model of the federation architecture including the federate&rsquo / s behavior model. The behavior model is based on Live Sequence Charts (LSCs), adopted as the behavioral specification formalism in the Federation Architecture Metamodel (FAMM). The FAMM is constructed conforming to metaGME, the meta-metamodel offered by Generic Modeling Environment (GME). FAMM serves as a formal language for describing federation architectures. We present a code generator that generates Java/AspectJ code directly from a federation architecture model. An objective is to help verify a federation architecture by testing it early in the development lifecycle. Another objective is to help developers construct complete federate applications. Our approach to achieve these objectives is aspect-oriented in that the code generated from the LSC in conjunction with the Federation Object Model (FOM) serves as the base code on which the computation logic is weaved as an aspect.

We present an approach based on Model-Driven Development ideas to create Software Product Lines(SPLs). In Model-Driven SPL approaches, the derivation of a product starts from a domain application model. This model is transformed through several stages reusing model transformation rules until a product is obtained. Transformations rules are selected according to variants included in configurations created by product designers. Configurations include variants from variation points, which are relevant characteristics representing the variability of a product line. Our approach (1) provides mechanisms to improve the expression of variability of Model-Driven SPLs by allowing designers to create fine-grained configurations of products, and (2) integrates a product derivation process which uses decision models and Aspect-Oriented Programming facilitating the reuse, adaptation and composition of model transformation rules. We introduce constraint models which make it possible for product line architects to capture the scope of product lines using the concepts of constraint, cardinality property and structural dependency property. To configure products, we create domain models and binding models, which are sets of bindings between model elements and variants and satisfy the constraint models. We define a decision model as a set of aspects. An aspect maintains information of what and when transformations rules that generate commonalities of products must be intercepted (joinpoints) and what transformation rules (advices) that generate variable structures must be executed instead. Our strategy maintains uncoupled variants from model transformation rules. This solves problems related to modularization, coupling, flexibility and maintainability of transformations rules because they are completely separated from variants; thus, they can evolve independently.

The overall contribution of this thesis is to propose an integrated approach for modeling and verifying the requirements of Self Adaptive Systems using Model Driven Engineering techniques. Model Driven Engineering is primarily concerned with reducing the gap between problem and software implementation domains through the use of technologies that support systematic transformation of problem level abstractions to software implementations. By using these techniques, we have bridged this gap through the use of models that describe complex systems at multiple levels of abstraction and through automated support for transforming and analyzing these models. We take requirements as input and divide it into Functional and Non Functional Requirements. We then use a process to identify those requirements that are adaptable and those that cannot be changed. We then introduce the concepts of Goal Oriented Requirements Engineering for modeling the requirements of Self Adaptive Systems, where Non Functional Requirements are expressed in the form of goals which is much more rich and complete in defining relations between requirements. We have identified some problems in the conventional methods of requirements modeling and properties verification using existing techniques, which do not take into account the adaptability features associated with Self Adaptive Systems. Our proposed approach takes into account these adaptable requirements and we provide various tools and processes that we developed for the requirements modeling and verification of Self Adaptive Systems. We validate our proposed approach by applying it on two different case studies in the domain of Self Adaptive Systems.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.

Reliability and safety of complex software-intensive systems are proved to be a crucial matter since most of these systems fulfil tasks, where a failure could lead to catastrophic consequences. For example, in space systems such as satellites, a failure could result in the loss of the satellite. Therefore, a certain level of reliability and safety must be assured for such systems to trust the services they provide. Standards set this level and put requirements for the analysis and assurance of these properties using documented evidence. In particular, European Cooperation for Space Standardization (ECSS) standards for space systems require Fault Tree Analysis(FTA) for identifying the causes of system failure and consequently safety hazards, as well as fault trees as evidence for the assurance of reliability and safety. In this thesis, we present a tool supported model-based approach to generate fault tree automatically from an existing system modelling and analysis toolset. CHESS is a system and dependability modelling toolset and integrates Concerto-FLA to enable the support of failure logic analysis. We proposed a model-based transformation from Concerto-FLA to fault tree model and implemented it as an Eclipse plugin in CHESS toolset. A case study is performed in the aerospace domain; more specifically we modelled Attitude Control System (ACS) and automatically generated IEC-61025-compliant fault trees. / AMASS project

En Interaction Homme-Machine, la qualité est une utopie : malgré toutes les précautions prises en conception, il existe toujours des utilisateurs et des situations d'usage pour lesquels l'Interface Homme-Machine (IHM) est imparfaite. Cette thèse explore l'auto-explication des IHM pour améliorer la qualité perçue par les utilisateurs. L'approche s'inscrit dans une Ingénierie Dirigée par les Modèles. Elle consiste à embarquer à l'exécution les modèles de conception pour dynamiquement augmenter l'IHM d'un ensemble de questions et de réponses. Les questions peuvent être relatives à l'utilisation de l'IHM (par exemple, "A quoi sert ce bouton ?", "Pourquoi telle action n'est pas possible ?) et à sa justification (par exemple, "Pourquoi les items ne sont-ils pas rangés par ordre alphabétique ?"). Cette thèse propose une infrastructure logicielle UsiExplain basée sur les méta-modèles UsiXML. L'évaluation sur un cas d'étude d'achat de voitures montre que l'approche est pertinente pour les questions d'utilisation de l'IHM. Elle ouvre des perspectives en justification de conception. / In Human-Computer Interaction, quality is an utopia. Despite all the design efforts, there are always uses and situations for which the user interface is not perfect. This thesis investigates self-explanatory user interfaces for improving the quality perceived by end users. The approach follows the principles of model-driven engineering. It consists in keeping the design models at runtime so that to dynamically enrich the user interface with a set of possible questions and answers. The questions are related to usage (for instance, "What's the purpose of this button?", "Why is this action not possible"?) as well as to design rationale (for instance, "Why are the items not alphabetically ordered?"). This thesis proposes a software infrastructure UsiExplain based on the UsiXML metamodels. An evaluation conducted on a case study related to a car shopping webiste confirms that the approach is relevant especially for usage questions. Design rationale will be further explored in the future.STAR

Le déploiement, la maintenance et l'évolution des systèmes d'informations techniques qui accompagnent les processus de création de produits (PLM) constituent des tâches complexes et parfois onéreuses pour des structures de type PME ou micro entreprise innovantes. Si l'appui sur un progiciel développé et maintenu par un éditeur permet aujourd'hui des solutions pérennes, la question de l'évolution conjointe des processus métiers de l'entreprise et du progiciel suite aux évolutions techniques de l'ingénierie numérique pose aux chercheurs la problématique des méthodologies à mettre en œuvre pour faciliter ce double axe d'évolution. Dans le cadre de ses démarches d'innovation, l'éditeur progiciel souhaite rendre accessibles à ses clients PME les capacités fonctionnelles de sa solution PLM en développant un atelier de modélisation pour la création de modèles métier au sein des systèmes PLM et la gestion de leur cohérence au cours du temps. Ce projet, réalisé dans le cadre d'une thèse CIFRE avec la société AUDROS, a pour but de fournir les concepts et les outils qui simplifient la synchronisation des différents outils métiers au sein du système d'information dans le but de gérer l'entreprise de façon la plus étendue et la plus homogène possible. / The specification, the deployment, the maintenance and the evolution of technical information systems which support the processes of products developement (PLM) constitute complex tasks for organisations like SME or innovative companies. If today the support on a software package developed and maintained by an editor allows long-lasting solutions, researchers face the issue of the convergent evolutions of the business processes and the software package. As the technical evolutions embedded in digital engineering, this thesis proposes methodologies to be implemented to facilitate this double axis of evolution. Within his innovation framework, the software editor wishes to provide his customers with PLM systems evolution tools.This project, granted as an industrial thesis with AUDROS company, aims at supplying the concepts and the tools which simplify the synchronization of the various business tools within the information system. The company can thus be dynamically supported in a context of extended enterprise.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.

A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação. / The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.