This thesis establishes a quantization noise model of a delta-sigma modulator (DSM), which is utilized to estimate the phase noise performance of a fractional-N frequency synthesizer. In delta-sigma modulator structures, we choose multi-stage noise shaping (MASH) and single-loop structure for investigating the advantages and disadvantages. We have implemented a 3rd order single-loop and a 3rd order MASH DSM by using Verilog codes and a Xilinx field-programmable gate-array (FPGA). With a reference frequency of 12MHz, the fractional-N frequency synthesizer has an output frequency band of 2400~2500MHz, and a frequency resolution of 183 Hz. The measured phase noise is lower than -54 dBc/Hz at 10 kHz offset frequency. The PLL settling time is less than 29us with a 48 MHz frequency hopping.

Abstract¡G For the fractional-N frequency synthesizers using delta-sigma modulation techniques, the noise source dominant to degrade the spectral purity comes from phase intermodulation of quantization noise due to the PLL nonlinearity. To study and improve the PLL nonlinearity effect, this thesis applies the theory of white quantization noise and nonlinear analysis method to simulate the frequency responses of quantization noises in delta-sigma modulators (DSM) with different order and in various architecture. With the help of Agilent EEsof¡¦s ADS tool, the phase noise performance of the studied fractional-N frequency synthesizers can be well predicted. For demonstration, this thesis work implements a 2.4 GHz fractional-N frequency synthesizer hybrid module, and measures the phase noise under considering various combinations of DSM order and architecture, PLL bandwidth and reference frequency. Another demonstration of this thesis is to implement a PLL IC using 0.18 £gm CMOS process. The implemented PLL IC operates in the frequency range from 2120 to 2380 MHz with a supply voltage of 1.8 V and a current consumption of 27 mA. Under the test condition of reference frequency and PLL bandwidth equal to 20 MHz and 50 kHz, respectively, the measured phase noise is 90 dBc/Hz at an offset frequency of 100 kHz and the measured stable time is about 40 £gs for a frequency jump of 80MHz.

Recently, there has been increasing interest within the potential user community of Global Positioning System (GPS) for high precision navigation problems such as aircraft non precision approach, river and harbor navigation, real-time or kinematic surveying. In view of more and more GPS applications, the reliability of GPS is at this issue. The Global Positioning System (GPS) is a space-based radio navigation system that provides consistent positioning, navigation, and timing services to civilian users on a continuous worldwide basis. The GPS system receiver provides exact location and time information for an unlimited number of users in all weather, day and night, anywhere in the world. The work in this thesis will mainly focuss on how to model a Mathematical expression for tracking GPS Signal using Phase Locked Loop filter receiver. Mathematical formulation of the filter are of two types: the first order and the second order loops are tested successively in order to find out a compromised on which one best provide a zero steady state error that will likely minimize noise bandwidth to tracks frequency modulated signal and returns the phase comparator characteristic to the null point. Then the Z-transform is used to build a phase-locked loop in software for digitized data. Finally, a Numerical Methods approach is developed using either MATLAB or Mathematica containing the package for Gaussian elimination to provide the exact location or the tracking of a GPS in the space for a given a coarse/acquisition (C/A) code.

The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation. / text

This thesis presents an investigation into the power transmission limitations imposed on a VSC-HVdc converter by ac system strength and ac system impedance characteristics, quantified by the short circuit ratio (SCR). An important result of this study is that the operation of the converter is not only affected by the SCR’s magnitude, but is also significantly affected by the ac system’s impedance angle at the fundamental frequency. As the ac impedance becomes more resistive, the minimum SCR required at the rectifier side increases from that required for ideally inductive ac impedance, but it decreases at the inverter side. The finite megavolt ampere (MVA) limit of the VSC imposes a further limitation on power transfer, requiring an increase in the value of the minimum SCR. This limitation can be mitigated if additional reactive power support is provided at the point-common-connection. A state-space VSC model was developed and validated with a fully detailed non-linear EMT model. The model showed that gains of the phased-locked-loop (PLL), particularly at low SCRs greatly affect the operation of the VSC-HVdc converter and that operation at low SCRs below about 1.6 is difficult. The model also shows that the theoretically calculated power-voltage stability limit is not attainable in practice, but can be approached if the PLL gains are reduced. The thesis shows that as the VSC-HVdc converter is subject to large signal excitation, a good controller design cannot rely on small signal analysis alone. The thesis therefore proposes the application of optimization tools to coordinate the controls of multiple converters in a dc grid. A new method, the "single converter relaxation method", is proposed and validated. The design procedure of control gains selection using the single converter relaxation method for a multi-converter system is developed. A new method for selecting robust control gains to permit operation over a range of operation conditions is presented. The coordination and interaction of control parameters of multi-terminal VSC are discussed. Using the SCR information at converter bus, the gain scheduling approach to optimal gains is possible. However, compared to robust control gains setting, this approach is more susceptible to system instability.

This thesis presents an investigation into the power transmission limitations imposed on a VSC-HVdc converter by ac system strength and ac system impedance characteristics, quantified by the short circuit ratio (SCR). An important result of this study is that the operation of the converter is not only affected by the SCR’s magnitude, but is also significantly affected by the ac system’s impedance angle at the fundamental frequency. As the ac impedance becomes more resistive, the minimum SCR required at the rectifier side increases from that required for ideally inductive ac impedance, but it decreases at the inverter side. The finite megavolt ampere (MVA) limit of the VSC imposes a further limitation on power transfer, requiring an increase in the value of the minimum SCR. This limitation can be mitigated if additional reactive power support is provided at the point-common-connection. A state-space VSC model was developed and validated with a fully detailed non-linear EMT model. The model showed that gains of the phased-locked-loop (PLL), particularly at low SCRs greatly affect the operation of the VSC-HVdc converter and that operation at low SCRs below about 1.6 is difficult. The model also shows that the theoretically calculated power-voltage stability limit is not attainable in practice, but can be approached if the PLL gains are reduced. The thesis shows that as the VSC-HVdc converter is subject to large signal excitation, a good controller design cannot rely on small signal analysis alone. The thesis therefore proposes the application of optimization tools to coordinate the controls of multiple converters in a dc grid. A new method, the "single converter relaxation method", is proposed and validated. The design procedure of control gains selection using the single converter relaxation method for a multi-converter system is developed. A new method for selecting robust control gains to permit operation over a range of operation conditions is presented. The coordination and interaction of control parameters of multi-terminal VSC are discussed. Using the SCR information at converter bus, the gain scheduling approach to optimal gains is possible. However, compared to robust control gains setting, this approach is more susceptible to system instability.

Στόχος της διπλωματικής εργασίας είναι η σχεδίαση ενός συστήματος που να επιτρέπει την μελέτη των τεχνικών Σύνθεσης Συχνοτήτων με βρόχο κλειδωμένης φάσης μέσω του RMCLab. Στη παρούσα διπλωματική εργασία μελετήθηκε και σχεδιάστηκε το κατάλληλο υλικό (hardware) και λογισμικό (software) έτσι ώστε να δίνεται η δυνατότητα μελέτης του βρόχου σύνθεσης συχνότητας χωρίς κανένα ουσιαστικό περιορισμό. Ο χρήστης του συστήματος που κατασκευάστηκε σ’ αυτή τη διπλωματική εργασία μπορεί να μελετήσει βρόχους σύνθεσης συχνοτήτων που υλοποιούνται με όλες τις γνωστές μέχρι σήμερα τεχνικές (πχ: Integer N, Fractional, ΣΔ), ή ακόμη να εφαρμόσει δικές του τεχνικές ή νέες, πρόσφατες τεχνικές όπως αυτή του DIPA. Μπορεί επιπλέον να σχεδιάσει και να χρησιμοποιήσει τους δικούς του διαιρέτες συχνότητας, τον δικό του phase/frequency comparator και ακόμη να επιλέξει μέσα από μία ευρεία περιοχή στοιχείων (αντιστάσεις πυκνωτές) για την υλοποίηση του φίλτρου του συνθέτη. Εκτιμούμε ότι το αποτέλεσμα αυτής της διπλωματικής εργασίας θα συμβάλει σημαντικά στην κατανόηση του βρόχου κλειδωμένης φάσης και του συνθέτη συχνοτήτων από τους φοιτητές, και επιπλέον θα διευκολύνει σημαντικά την υλοποίηση και πειραματική επιβεβαίωση νέων διατάξεων βασισμένων σε βρόχο κλειδωμένης φάσης. / The aim of this dissertation is the development and implementation of the appropriate hardware and software for enabling the study of the PLL based frequency synthesis techniques using the facilities of the RMCLab (Remote Monitored and Controlled Lab.). The RMCLab user is now able to study deeply on the well known techniques of frequency synthesis as Integer N, Fractional or ΣΔ, since the developed system enables him to access and customize any of the synthesizer components (dividers, phase/frequency detector, filter). Additionally, the system allows the user to apply new appeared frequency synthesis techniques such as the DIPA technique, or even to develop and experiment on his own ideas regarding frequency synthesis. It is anticipated that the system developed under this dissertation will enable students to deeply understand on the theory of phase locked loop and practice on various frequency synthesis techniques.

Αντικείμενο της παρούσης διπλωματικής εργασίας είναι ο σχεδιασμός ενός συνθέτη συχνοτήτων για MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB εφαρμογές. Ο συνθέτης συχνοτήτων αποτελεί εξέχουσας σημασίας δομικό στοιχείο των RF πομποδεκτών αφού είναι υπεύθυνος για την παραγωγή του (LO oscillator) σήματος που οδηγεί τον downconverter και τον upconverter στο μονοπάτι του δέκτη και του πομπού αντίστοιχα. Μελετήθηκαν οι δομές, οι κυριότερες τοπολογίες και τα χαρακτηριστικά ενός τυπικού συνθέτη συχνοτήτων καθώς και τα κύρια εξαρτήματα που το απαρτίζουν. Αφού μελετήσαμε το βασικό και το εναλλακτικό σχέδιο συχνοτήτων όπως παρουσιάζεται από το MB-OFDM πρότυπο προτείναμε την κατάλληλη τοπολογία η οποία και διαφέρει από αυτή των τυπικών συνθετών συχνοτήτων που χρησιμοποιούνται ευρέως στα ασύρματα συστήματα τηλεπικοινωνιών λόγω των υψηλών απαιτήσεων της UWΒ τεχνολογίας. Η επιλογή των εξαρτημάτων που απαρτίζουν τον συνθέτη συχνοτήτων έγινε με βάση την ελαχιστοποίηση του θορύβου φάσης και της κατανάλωσης ισχύος, της εξάλειψης ανεπιθύμητων σημάτων στην έξοδό του, τα οποία μπορούν να δημιουργήσουν παρεμβολές σε άλλα τηλεπικοινωνιακά συστήματα καθώς και την επίτευξη μικρού χρόνου αποκατάστασης που απαιτεί ένας τέτοιος συνθέτης. Προτείνεται και εξομοιώθηκε λοιπόν συνθέτης συχνοτήτων με περιοχή λειτουργίας του από 3.1 έως 10.6 GHz με βήμα συχνότητας 528 MHz όπως αυτή ορίζεται από το πρότυπο 802.15.3 που αναφέρεται στην UWB τεχνολογία. Από τα αποτελέσματα της εξομοίωσης προκύπτει ότι επιτυγχάνεται χαμηλός θόρυβος φάσης, μικρός χρόνος αποκατάστασης και μικρή ισχύς των ανεπιθύμητων σημάτων, αποτελέσματα που συνάδουν με τις απαιτήσεις της UWB τεχνολογίας. Τέλος προτείνεται και υλοποιείται η πλακέτα του βρόχου κλειδωμένης φάσης ο οποίος και αποτελεί το βασικό δομικό στοιχείο του συνθέτη συχνοτήτων. / The subject of the present essay is the design of a frequency synthesizer for MB-OFDM (Multiband Orthogonal Frequency-Division Multiplexing) UWB applications. The frequency synthesizer is a structural part of foremost importance at the RF transceivers, as it is responsible for the production of the signal (LO oscillator) that leads the downconverter and the upconverter at the path of the receiver and the transmitter correspondingly. Structures, principal topologies and a typical’s frequency synthesizer characteristics have been studied, as well as the main components that compose it. After having studied the current and the alternate frequency plan –as presented by MB-OFDM standard-, we proposed the proper topology, which is different from the one for the typical frequency synthesizers, that are widely used at the RF communication systems, due to UWB technology’s high specifications. The choice of the components that compose the frequency synthesizer is based on the minimization of the phase noise and the power consumption, on the reduction of spurious signals during its entrance, which can create interferences to other communicational systems, as well as on the accomplishment of a short settling time, which a synthesizer of this kind demands. So, a frequency synthesizer with a frequency range from 3.1 to 10.6 GHz, with a frequency step of 528 MHz -as it is defined from the standard 802.15.3 that is referred at UWB technology-, has been proposed and simulated. From the results of the simulation, it emerges that a low phase noise is accomplished, a short settling time and a low power of spurious signals, results that add up to UWB technology’s specifications. Finally, the PCB (printed circuit board) of the phase locked loop - which consists the basic structural part of the frequency synthesizer - has been proposed and implemented.

Στην παρούσα Διπλωματική Εργασία μελετάται η αρχιτεκτονική και τα χαρακτηριστικά ενός νέου συνθέτη συχνοτήτων (Frequency Synthesizer) που βασίζεται στην τεχνική του βρόχου κλειδωμένης φάσης (Phase-Locked Loop). Η νέα αρχιτεκτονική ξεπερνά την δυσκολία του απλού συνθέτη συχνοτήτων να έχει ταυτόχρονα μικρό βήμα συχνότητας και μικρό χρόνο κλειδώματος, ενώ ταυτόχρονα διατηρεί και επαυξάνει την δυνατότητα των απλών συνθετών να απορρίπτουν τον θόρυβο φάσης, δίνοντας έτσι πολύ καλή ποιότητα σήματος εξόδου. Τα χαρακτηριστικά αυτά καθιστούν τον νέο συνθέτη πολύ ανταγωνιστικό. / This Diploma Thesis studies the architecture and the characteristics of a new Frequency Synthesizer which based on the Phase-Locked Loop technique. This new architecture overcomes the difficulty of the simple frequency synthesizer to have simultaneously small frequency step and small locking time, while maintains and enhances the possibility to reject phase noise. This concludes to the high quality of the output signal. The above characteristics make the new synthesizer very competitive.

As redes de distribuição de sinais de tempo - ou redes de sincronismo - têm a tarefa de distribuir os sinais de fase e freqüência ao longo de relógios geograficamente dispersos. Este tipo de rede é parte integrante de inúmeras aplicações e sistemas em Engenharia, tais como sistemas de comunicação e transmissão de dados, navegação e rastreamento, sistemas de monitoração e controle de processos, etc. Devido ao baixo custo e facilidade de implementação, a topologia mestre-escravo tem sido predominante na implementação das redes. Recentemente, devido ao surgimento das redes sem fio - wireless - de conexões dinâmicas, e ao aumento da freqüência de operação dos circuitos integrados, topologias complexas, tais como as redes mutuamente conectadas e small world têm ganhado importância. Essencialmente cada nó da rede é composto por um PLL - Phase-Locked Loop - cuja função é sincronizar um oscilador local a um sinal de entrada. Devido ao seu comportamentamento não-linear, o PLL apresenta um jitter com o dobro da freqüência de livre curso dos osciladores, prejudicando o desempenho das redes. Dessa forma, este trabalho tem como objetivo o estudo analítico e por simulação das condições que garantam a existência de estados síncronos, e do comportamento do jitter de fase nas redes de sincronismo. São analisadas as topologias mestre-escravo e mutuamente conectada para o PLL analógico clássico. / Network synchronization deals with the problem of distributing time and fre- quency among spatially remote locations. This kind of network is a constituent element of countless aplications and systems in Engineering, such as communication and data transmission systems, navigation and position determination, monitoring and process control systems, etc. Due to its low cost and simplicity, the master-slave architec- ture has been widely used. In the last few years, with the growth of the dynamically connected wireless networks and the rising operational frequencies of the integrated cir- cuits, the study of the mutually connected and small world architectures are becoming relevant. Essentially, each node of a synchronization network is constituted by a PLL - Phase-Locked Loop - circuit that must automatically adjust the phase of a local oscillator to the phase of an incoming signal. Because of its nonlinear behavior the PLL presents a phase jitter with the double of the free running frequency of the oscillators, impairing the network performance. Thus, this work aims to study, both analytically and by simulation, the existence conditions of the synchronous states and the behavior of the double frequency jitter in the synchronization networks. Specifically the One Way Master Slave (OWMS) and Mutually Connected (MC) network architectures for classical analogical PLLs are analyzed.