The first topic of the thesis presents an NTSC digital video decoder which is designed by using two lines delay comb filter to decode the luminance signal (Y) and the chrominance signal (C). The coefficients of the low pass filter are tuned properly to reduce the gate count without losing any original performance of the chroma demodulator. The second topic of the thesis is to propose a method and a circuitry to resolve the out-of-phase problem between the color burst and the sub-carrier in NTSC TV receivers. The feature of the method is that a delay means is inserted which leads to the synchronization of the color burst and the sub-carrier such that the following color demodulator is able to extract right color signals. Besides, the locking of the two signals will be fastened without any extra large circuit cost.

This thesis is composed of three parts. In the first part, analysis and discussion of phase noise in phase-locked loop is made. Because OFDM upconverter requires high phase noise performance, we therefore study the mechanism of noise suppression in a proposed dual phase-locked loop, and then derive the formula to predict the circuit characteristics. In the second part, experiment and simulation of a dual phase-locked loop is performed for comparison. The experiment uses hybrid circuit combined with related equipment and components to measure the noise suppression characteristics in a dual phase-locked loop. The simulation relies on the component behavioral model in ADS. Comparison between simulation and measurement shows good agreement. In the third part, this thesis carries out a 1.55¡V2.3 GHz frequency synthesizer RFIC design for DVB up-down architecture using TSMC 0.18£gm CMOS process. The test results validate the chip design.

Cooling fans, widely used in desktop and laptop computers, have been designed toward the tendency of low noise and low consumption power. This thesis purposes a efficient low-noise double-loop control method to regulate the fan speed according to environmental temperature. The proposed controller consists of three parts. The first part is a command generator which generates a train of pulses with its frequency varying proportionally with temperature. The second part is a phase locked loop which intends to synchronize the command pulses with the pulses fed back from the Hall IC of the motor. The third part is an inner loop quantized control that switches the fan according to the error signal sent by the phase locked loop. This double-loop design of feedback achieves accurate fan speed regulation with the nice properties of low noise and high efficiency. The experimental results show an average regulation error of 0.4188% in the fan speed range of 306.6~1953 R.P.M which corresponds to the temperature range 10~70 Celsius.

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

The work deals with design, simulation and preparation of laboratory preparation. The main aim of the thesis is to design and implement a simple noise generator, signal sources, mixer and phase lock loop for teaching purposes.

The aim of the master thesis is on lock-in amplifiers. Amplifier's basic parts and lock-in circuits description is listed in introductory chapters. The thesis offers overview of parameters of chosen devices available on the market and their possible usage. We describe HF2LI device functions and usage of ziControl software. With the aim to verify properties of the device and ziControl software, one of the last chapters focuses on manipulation with HF2LI device. The conducted experiments and achieved results are presented in the last chapter.

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Master of Science / Department of Electrical and Computer Engineering / Andrew Rys / Clock and data recovery (CDR) circuits form the backbone of high speed receivers. These receivers are used in various applications such as chip to chip interconnects, optical communications and backplane routing. The received data in CDR circuits are potentially noisy and asynchronous, i.e. they are not accompanied by a clock. The CDR circuit has to generate a clock from the data and then retime the data. The CDR circuit that recovers the clock and retimes the data has to remove the jitter that is accumulated during its transport through channels due to inter symbol interference (ISI). There are stringent jitter specifications defined by various communication standards that must be addressed by CDR circuits. These make the design of CDR circuits more difficult for system designers as well the circuit designer. Many parameters have to be taken into consideration while designing a CDR circuit. The problem becomes even more interesting as there are various tradeoffs in the design. As speeds of communications increase, the maximum allowable jitter decreases. Jitter in CDR circuits arises due to a lot of factors and is also dependent on the method used for clock and data recovery. In CDR circuits that use phase locked loops to recover the clock and retime the data, jitter may be caused by the metastability of sequential elements used in phase detectors. Jitter is also caused by the phase noise of the VCO used in the PLL. In CDR circuits that use the delay locked loop to recover the clock and data, jitter may be caused by the metastability of sequential elements in phase detectors as well as the quality of reference clock that is used to re-time the data. Additional effects that can cause jitter in CDR circuits include the use of spread spectrum clocking, delta sigma noise shaping performance, etc. In this thesis a non-sequential linear phase detector has been proposed which does not use any sequential elements to avoid metastability issues in phase detectors. The output jitter in a CDR circuit that uses the proposed phase detector is measured and compared to a Hogge Phase Detector [5].

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The U.S. Army’s Hardened Subminiature Telemetry and Sensor Systems (HSTSS) program has engaged the M/A-COM Corporation to work in the development of a highly accurate, crystal controlled telemetry transmitter chip set to be used in Army and other U.S. military munitions. A critical factor in this work is the operating environment of up to 100,000-g launch accelerations. To support the Army in this project, M/A-COM is developing integrated Voltage Controlled Oscillators (VCO) for L and S band, a silicon synthesizer/phase locked loop (PLL) IC, and a family of power amplifiers. Lastly, the transmitter module will be miniaturized and hardened using M/A-COM’s latest chip-onboard mixed technology manufacturing capabilities. This new chip set will provide the telemetry engineer with unprecedented design flexibility. This paper will review the overall transmitter system design and provide an overview for each functional integrated circuit.