Este trabalho propÃe o desenvolvimento de uma fonte de alimentaÃÃo portÃtil para notebooks e outros equipamentos eletrÃnicos usando energia fotovoltaica. O sistema completo à composto por dois mÃdulos fotovoltaicos poli-cristalinos de 54W conectados em paralelo; um conversor boost clÃssico usado para controlar a carga das baterias de chumbo-Ãcido reguladas a vÃlvula (VRLA-Valve Regulated Lead Acid) de 40 Ah associadas em sÃrie formando um barramento de 24Vcc e um conversor boost-flyback que tem a funÃÃo de elevar a tensÃo do banco de baterias de 24Vcc a uma tensÃo de saÃda de 250Vcc. O conversor boost utiliza o algoritmo perturba e observa (P&O) para conseguir o ponto de mÃxima potÃncia dos mÃdulos fotovoltaicos. Por outro lado, no conversor boost-flyback que opera em modo de conduÃÃo contÃnua (MCC) à usada a tÃcnica de controle por corrente de pico. Para verificar o princÃpio de funcionamento da fonte de alimentaÃÃo de dois estÃgios, o primeiro estÃgio foi desenvolvido com potÃncia de saÃda de 120W e o segundo estÃgio com potÃncia de saÃda de 200W. / This study proposes the development of a portable power supply to feed notebook computers and other electronic equipment using photovoltaic energy. The complete system is composed by two polycrystalline photovoltaic modules of 54W in parallel, a classic boost converter that allows to work the photovoltaic modules in the maximum power point (MPP) and to charge two lead-acid valve regulated batteries (VRLA Valve-Regulated Lead Acid) of 40Ah associates in series to form a bus of 24Vcc, and a boost-flyback converter that has as function to raise the battery bank voltage of 24Vcc to output voltage of 250Vcc. The boost converter uses the algorithm perturb and observe (P&O) to track the maximum power point of the photovoltaic modules. On the other hand, in the boost-flyback converter operates in continuous conduction mode (CCM) using peak current mode control technique to regulate the output voltage. To verify the feasibility of the two stage power supply, was developed a prototype with first stage of 120W output power, and the second stage of 200W output power.

Power consumption is a major concern for modern processors. Voltage scaling is one of the most effective mechanisms to reduce power consumption. However, voltage scaling is limited by large memory structures, such as caches, where many cells can fail at low voltage operation. As a result, voltage scaling is limited by a minimum voltage (Vccmin), below which the processor may not operate reliably. Researchers have proposed architectural mechanisms, error detection and correction techniques, and circuit solutions to allow the cache to operate reliably at low voltages. Architectural solutions reduce cache capacity at low voltages at the expense of logic complexity. Circuit solutions change the SRAM cell organization and have the disadvantage of reducing the cache capacity (for the same area) even when the system runs at a high voltage. Error detection and correction mechanisms use Error Correction Codes (ECC) codes to keep the cache operation reliable at low voltage, but have the disadvantage of increasing cache access time. In this thesis, we propose a novel architectural technique that uses spare cache blocks to back up a set-associative cache at low voltage. In our mechanism, we perform memory tests at low voltage to detect errors in all cache lines and tag them as faulty or fault-free. We have designed shifter and adder circuits for our architecture, and evaluated our design using the SimpleScalar simulator. We constructed a fault model for our design to find the cache set failure probability at low voltage. Our evaluation shows that, at 485mV, our designed cache operates with an equivalent bit failure probability to a conventional cache operating at 782mV. We have compared instructions per cycle (IPC), miss rates, and cache accesses of our design with a conventional cache operating at nominal voltage. We have also compared our cache performance with a cache using the previously proposed Bit-Fix mechanism. Our result show that our designed spare cache mechanism is 15% more area efficient compared to Bit-Fix. Our proposed approach provides a significant improvement in power and EPI (energy per instruction) over a conventional cache and Bit-Fix, at the expense of having lower performance at high voltage.

A comparative study of the economic benefits that can be obtained from different degrees of power factor correction for medium and small scale industrial installations is shown. A new approach for precise calculation of kws and kvars required at different power factors is presented. These calculated values are used to find the return on investments for the capacitors needed for power factor correction. The developed method is easy to use, cost effective, accurate and will help electrical engineers with minimum knowledge of power systems to precisely determine the savings available by improving the power factor of an industrial load.

This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques. / Graduation date: 2012

Many methods for EMI suppression have been developed in the last fifty years, most of them, showing a hardly change in its implementation. Traditional tools for EMI suppression are related to the use of filters, shielding techniques and new methods for layout improvement. These hardware techniques are normally supported with waveform shapes having themselves a lower spectral content. This kind of signals makes part of a different concept of EMI suppression that consists of limiting the spectral content in the signal itself. When possible, just waveforms with a lower spectral content should be used, this way making easier, simpler and cheaper the use of filters and other suppression means. In this line, EMI-reduction techniques such a Spread Spectrum Clock Generation (SSCG) are contributing to eliminate or limit the problem at the root, that is, at the signal itself.This thesis is developed in several parts, corresponding to different chapters. A summary of these chapters is presented onwards:After introduction in chapter 1, a wide theoretical development of the modulation and related concepts are presented in chapter 2. It is explained generically all aspects related to the modulation and particularly, to the frequency modulation. Main parameters of frequency modulation are presented and explained in detail and how practical considerations may affect to the theoretical behaviour of these parameters. Because the theoretical part of this thesis is completely based on the fundamentals of Fourier Transform, a sufficient explanation was thought to include for its right understanding . Finally, all this knowledge is summarized in a computational algorithm (MATLAB environment), capable of generating any frequency modulation of a sinusoidal carrier and the corresponding spectral components resulting from the modulation process.Chapter 3 takes profit of the results obtained in Chapter 2 where it is possible to obtain the theoretical behaviour of the different modulation profiles of interest: sinusoidal, triangular, exponential and mixed waveforms. This way, chapter 3 is intended to completely understand and analyze the theoretical behaviour of these modulation profiles and be quantified according to several significant measure parameters. Afterwards, a comparison of these modulation profiles is carried out by means of the measure parameters defined previously. A proposal of control for a real power converter and theoretical considerations to apply a certain SSCG method to switching power converters are also included in this chapter. After all aspects of frequency modulation by means of SSCG methods have been theoretically developed, it is mandatory the verification of the theoretical conclusions through an experimental test plant. Chapter 4 starts with the description, theoretical calculation and physical implementation of this test plant. Most practical considerations are here dealt with, like the influence of the Spectrum Analyzer's Resolution Bandwidth (RBW) on the measured EMI, a proposal of a practical method to select a valuable SSCG technique applied to Switching Power Converters, comparative measurements of conducted EMI within the range of conducted emissions (0 Hz 30 MHz) and a proposal about SSCG as a method to avoid interfering a certain signal.Chapter 5 summarizes the whole conclusions gathered through the previous chapters and, finally, chapter 6 lists references related to the thesis, separated into different thematic groups.

Modern arc welding machines utilize controllable high frequency DC/DC power supply with high dynamic and steady state current regulation performance. In the design robustness, small size and low weight, low complexity, and high efficiency are the defining criteria. The most suitable approach for a 5 kW arc welding machine power supply application is the high frequency Full-Bridge Phase-Shifted Zero Voltage Switching (FB-PS-ZVS) DC/DC converter with an isolation transformer. This converter not only gives the advantage of zero voltage switching for a wide load current range, it also provides reduced Electromagnetic Interference (EMI) and reduced component stress compared to standard PWM converters. In this thesis a FB-PS-ZVS DC/DC converter with 5 kW power rating is designed for modern arc welding machine applications. IGBTs are utilized at 50 kHz switching frequency for high efficiency and control bandwidth. The output current of the DC/DC converter is controlled via a Digital Signal Processor (DSP) control platform. The performance of the designed DC/DC converter is evaluated via the computer simulations and the experimental study of the constructed prototype.

In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.

Power has become an important design closure parameter in today’s ultra low submicron digital designs. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters or voltage regulators design, system, board and package thermal analysis, power grid design and signal integrity analysis to minimizing power itself. This work focuses on challenges arising due to increase in power to power grid design and analysis. Challenges arising due to lower geometries and higher power are very well researched topics and there is still lot of scope to continue work. Traditionally, designs go through average IR drop analysis. Average IR drop analysis is highly dependent on current dissipation estimation. This work proposes a vector less probabilistic toggle estimation which is extension of one of the approaches proposed in literature. We have further used toggles computed using this approach to estimate power of ISCAS89 benchmark circuits. This provides insight into quality of toggles being generated. Power Estimation work is further extended to comprehend with various state of the art methodologies available i.e. spice based power estimation, logic simulation based power estimation, commercially available tool comparisons etc. We finally arrived at optimum flow recommendation which can be used as per design need and schedule. Today’s design complexity – high frequencies, high logic densities and multiple level clock and power gating - has forced design community to look beyond average IR drop. High rate of switching activities induce power supply fluctuations to cells in design which is known as instantaneous IR drop. However, there is no good analysis methodology in place to analyze this phenomenon. Ad hoc decoupling planning and on chip intrinsic decoupling capacitance helps to contain this noise but there is no guarantee. This work also applies average toggle computation approach to compute instantaneous IR drop analysis for designs. Instantaneous IR drop is also known as dynamic IR drop or power supply noise. We are proposing cell characterization methodology for standard cells. This data is used to build power grid model of the design. Finally, the power network is solved to compute instantaneous IR drop. Leakage Power Minimization has forced design teams to do complex power gating – multilevel MTCMOS usage in Power Grid. This puts additonal analysis challenge for Power Grid in terms of ON/OFF sequencing and noise injection due to it. This work explains the state of art here and highlights some of the issues and trade offs using MTCMOS logic. It further suggests a simple approach to quickly access the impact of MTCMOS gates in Power Grid in terms of peak currents and IR drop. Alternatively, the approach suggested also helps in MTCMOS gate optimization. Early leakage optimization overhead can be computed using this approach.

Power supply noise, which is the variation in the supply voltage across the on-die supply terminals of VLSI circuits, is a serious performance degrader in digital circuits and mixed analog-digital circuits. In digital VLSI systems, power supply noise causes timing errors such as delays, jitter, and false switching. In microprocessors, power supply noise reduces the maximum operating frequency (FMAX) of the CPU. In mixed analog-digital circuits, power supply noise manifests as the substrate noise and impairs the performance of the analog portion. The decrease in the available noise margin with the decrease in the feature size of transistors in CMOS systems makes the power supply noise a very serious issue, and demands new methods to reduce the power supply noise in sub-micron CMOS systems. In this thesis, we develop a new method to determine optimal time-delays between the switching of input/output (I/O) data buffers in digital VLSI systems that realizes maximum reduction of the power supply noise. We first discuss methods to characterize the distributed nature of the Power Delivery Network (PDN) in the frequency-domain. We then develop an analytical method to determine the optimal delays using the frequency-domain response of the PDN and the supply current spectrum of the buffer units. We explain the mechanism behind the cancellation of the power supply noise by the introduction of optimal buffer-to-buffer delays. We also develop a numerical method to determine the optimal delays and compare it with the analytical method. We illustrate the reduction in the power supply noise by applying the optimal time-delays determined using our methods to two examples of PDN. Our method has great potential to realize maximum reduction of power supply noise in digital VLSI circuits and substrate noise in mixed analog-digital VLSI circuits. Lower power supply noise translates into lower cost and improved performance of the circuit.

Ein wirtschaftlich optimal ausgelegtes Magnetschwebebahnsystem kann zur Lösung der weltweit drohenden Verkehrsprobleme beitragen, die im Zuge von Globalisierung und steigender Bevölkerung vor allem Regionen mit hohem Wachstumspotential bevorstehen. Im Grenzbereich zwischen Technikbewertung und Wirtschaftlichkeitsbetrachtung werden in der vorliegenden Forschungsarbeit einerseits Optimierungsansätze für das Subsystem „Antrieb und Energieversorgung“ des Transrapid vorgestellt. Sie leisten einen Beitrag zur Erhöhung der Wirtschaftlichkeit des Gesamtsystems über den Lebenszyklus. Auf der anderen Seite wird eine Methodik präsentiert, die es ermöglicht, die betriebswirtschaftlichen Wirkungen der einzelnen Optimierungsmaßnahmen für das Gesamtsystem abzuschätzen. Ausgangspunkt der Untersuchungen ist die Analyse von Zielsystem und aktuellem Entwicklungsstand des Transrapid-Systems. Darauf aufbauend lassen sich mögliche Optimierungsschwerpunkte für das Teilsystem „Antrieb und Energieversorgung“ ableiten und Varianten in Abhängigkeit der Auslegungsparameter erstellen. Kernstück der vorliegenden Ausarbeitung ist die Erstellung einer Optimierungsstrategie, die eine makroskopische Bewertung der Optimierungsansätze ermöglicht. Dies ist erforderlich, da sämtliche Optimierungen stark divergierende Auswirkungen auf die Betriebswirtschaftlichkeit des Gesamtsystems haben - neben den Kosten werden über die Leistungsfähigkeit auch die Erlöse eines Projekts beeinflusst. Basis der Strategie ist die Verknüpfung von Kostenänderungsfaktoren mit Leistungsfähigkeitsparametern. Infolgedessen wird im Ergebnis der Arbeit ein Werkzeug geschaffen, das unter projektspezifischen Randbedingungen als Entscheidungshilfe zur Auslegung des Transrapid-Subsystems „Antrieb und Energieversorgung“ dient.