Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital LDOs have become a more attractive design choice since they avoid the difficulty of designing high-gain amplifiers with low voltage. This thesis investigates techniques for both modeling and enhancement of digital LDO transient response. It discusses the importance of the resistance in the output stage of an LDO, and proposes a simulation model for examining LDO transient response. In addition, the thesis studies circuit techniques to improve LDO transient response. Different LDO circuits are implemented and compared in this study.

In order to meet demands for faster and more efficient data processing, modern microprocessors are being designed with lower voltage implementations. The processor voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be packed on a single processor chip, and processors will operate at higher frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power management. Future generation processors will draw current up to 50 A ~ 100 A [2]. These demands, in turn, will require special power supplies and Voltage Regulator Modules (VRMs) to provide lower voltages with higher currents and fast transient capabilities for microprocessors. This work presents several low-voltage high-current VRM technologies for future generation data processing, communication, and portable applications. The developed advanced VRMs with these new technologies have advantages over conventional ones in power density, efficiency, transient response, reliability, and cost. The multi-module interleaved quasi-square-wave VRM topology achieves a very fast transient response and a very high power density. This topology significantly reduces the filter inductance and capacitance, while having small output and input ripples. The analysis, design, and experimental verification for this new topology are presented in this work. The current sensing and current sharing techniques are developed with simple and cost-effective implementations. With this technique, traditional current transformers and sensing resistors are not required, and the inductance value, MOSFET on resistance and other parasitics have no effect on current sharing results. The design principles are developed and experimentally verified. A generalized approach and an extension of the novel current sharing control are presented in this work. The techniques for improving VRM light load efficiency are developed in this work. By utilizing the duty cycle signal, VRMs can be implemented with advanced power management functions to reduce further the power consumption at light loads to extend the battery-operation time in portable systems or to facilitate the compliance with various "energy star" ("green" power) requirements in office systems. Four improved approaches are presented and verified with experimental results. The high-input-voltage VRM topology, push-pull forward converter, can be used in high-bus-voltage distributed power systems. This converter has a high efficiency, a high power density, a fast transient response, and can be easily packaged as a standard module. The circuit design and experimental evaluation are addressed to demonstrate the operation principles and advantages of this topology. / Ph. D.

To support the increasingly demanding requirements for power conversion units, a digitally controlled dual output stage buck converter is designed. The system consists of a dual output stage, which includes an auxiliary buck output stage connected in parallel with a main output stage. The auxiliary output stage is only active during load transient to suppress the output voltage variation. A digital controller is designed to control both stages with a linear/nonlinear control scheme. Nonlinear control is applied during load transient based on the capacitor charge balance principle; whereas linear PID control governs the steady state operation. The design is verified with simulation and experimentally with discrete components. The controller is realized with a FPGA with preset output stage parameters. The experimental result shows a 60% reduction of output voltage variation for a heavy-to-light load transient.

To support the increasingly demanding requirements for power conversion units, a digitally controlled dual output stage buck converter is designed. The system consists of a dual output stage, which includes an auxiliary buck output stage connected in parallel with a main output stage. The auxiliary output stage is only active during load transient to suppress the output voltage variation. A digital controller is designed to control both stages with a linear/nonlinear control scheme. Nonlinear control is applied during load transient based on the capacitor charge balance principle; whereas linear PID control governs the steady state operation. The design is verified with simulation and experimentally with discrete components. The controller is realized with a FPGA with preset output stage parameters. The experimental result shows a 60% reduction of output voltage variation for a heavy-to-light load transient.

Swelling of a polymer gel is a kinetic process coupling mass transport and mechanical deformation. A comparison between a nonlinear theory for polymer gels and the classical theory of linear poroelasticity is presented. It is shown that the two theories are consistent within the linear regime under the condition of a small perturbation from an isotropically swollen state of the gel. The relationships between the material properties in the linear theory and those in the nonlinear theory are established by a linearization procedure. Both linear and nonlinear solutions are presented for swelling kinetics of substrate-constrained and freestanding hydrogel layers. A new procedure is suggested to fit the experimental data with the nonlinear theory. A nonlinear, transient finite element formulation is presented for initial boundary value problems associated with swelling and deformation of hydrogels, based on nonlinear continuum theories for hydrogels with compressible and incompressible constituents. The incompressible instantaneous response of the aggregate imposes a constraint to the finite element discretization in order to satisfy the LBB condition for numerical stability of the mixed method. Three problems of practical interests are considered: constrained swelling, flat-punch indentation, and fracture of hydrogels. Constrained swelling may lead to instantaneous surface instability. Indentation relaxation of hydrogels is simulated beyond the linear regime under plane strain conditions, and is compared with two elastic limits for the instantaneous and equilibrium states. The effects of Poisson’s ratio and loading rate are discussed. On the study of hydrogel fracture, a method for calculating the transient energy release rate for crack growth in hydrogels, based on a modified path-independent J-integral, is presented. The transient energy release rate takes into account the energy dissipation due to diffusion. Numerical simulations are performed for a stationary center crack loaded in mode I, with both immersed and non-immersed chemical boundary conditions. Both sharp crack and blunted notch crack models are analyzed over a wide range of applied remote tensile strains. Comparisons to linear elastic fracture mechanics are presented. A critical condition is proposed for crack growth in hydrogels based on the transient energy release rate. The applicability of this growth condition for simulating concomitant crack propagation and solvent diffusion in hydrogels is discussed. / text

[pt] Testes de relés de proteção têm assumido maior importância como resultado dos avanços tecnológicos. Novos relés podem ser projetados para atuarem rápido, sendo particularmente sensíveis a parte transitória da falta que eles supostamente detetam. Procedimentos usuais para testes de relés utilizam arquivos obtidos durante testes de falta, ou através de programas de simulação como o EMTP. Entretanto é muito difícil caracterizar um conjunto de formas de onda como suficiente para testes de relés. Como conseqüência, [16] sugeriu o uso de um procedimento do tipo Monte-Carlo para gerar ondas de modo a cobrir a maior parte das possíveis situações de transitório. Nesta metodologia, a linha de transmissão sob condição de falta é alimentada por um sistema equivalente fictício consistindo de um gerador de potência com uma impedância RLC. Quando a falta ocorre, o sistema oscila em determinadas freqüências. Estas freqüências são utilizadas para caracterizarem a forma de onda da falta. Neste trabalho um método de simulação de ondas viajantes é utilizado, baseado em filtros digitais, objetivando operação em tempo real. Como resultado, foi desenvolvido um procedimento de síntese do sistema fictício utilizando linhas de transmissão sem perdas ao invés de redes RLC. O software roda num computador tipo IBM PC tendo uma placa DSP baseada no chip TMS320C25. Os parâmetros da linha são calculados no PC e transferidos para a placa DSP, aonde a simulação é realizada em tempo real. Para casos com somente uma linha de transmissão, tal sistema trabalha com uma freqüência de amostragem de 4080 Hz representando transitórios de falta até 2040 Hz. Simulação OFF-LINE é também disponível para oferecer uma base de comparação entre a implementação em ponto fixo do DSP e a versão em ponto flutuante. Comparação com outro procedimento de simulação OFF-LINE é também apresentado com boa precisão entre os procedimentos ON-LINE e OFF-LINE. / [en] The testing of protective relays has become more and more important as result of technological advances. New relays may be designed to act fast, being particularly sensitive to the transient part of the fault supposed to be detected. A common procedure is either the use of real recorded faults during tests, or simulating these faults by computer programs, such as the EMP. However, it is difficult to characterize a unique set of transient waveforms sufficientfor the tests. As a consequence, it was suggested [16] the use of a Monte-Carlo type of procedure to generate waveforms in order to cover most of the possible transient situations. In this approach, the faulted transmission line is simulated, being fed by a fictitious equivalent system consisting of a power generator with an RLC load. When the fault occurs, there is resonance at particular chosen frequencies. These frequencies are used to characterize the fault waveform. In this work a travelling wave method of simulation is used, based on digital filters, looking for real time operation. As a result, it was developed a synthetic procedure for generating the fictitious system using lossless transmission lines instead of RLC networks. The software runs on a IBM PC type computer having a DSP board based on a TMS320C25. The transmission line parameters are evaluated in the PC and transferred to the DSP board, where real time the simulation is performed. For cases with only one lossless transmission line, the system works with a sampling frequency of 4.08 KHz, representing fault transients up to 20.04 KHz. Off-line simulation is available as well, primarily to offer a comparison basis between the fixed point DSP implementation and a floating point version. Comparison with other off-line simulation procedures are also presented with good agreemment between on-line and off-line procedures.

With the electronic equipments becoming more and more complicated, the requirements for the power management are more and more strict. Efficient performance, high functionality, small profile, fast transient and low cost are the most wanted features for modern power management ICs, especially for mobile power. In order to reduce profile, the number of external components should be as small as possible, which means that compensator, ramp compensation, current sensor, driver and even power devices should be all implemented on a single chip, i.e. monolithic integration. Comparing with discrete switching DC-DC converter, monolithic integration brings a number of benefits and new design challenges. Besides monolithic integration, high switching frequency is another trend for power management ICs due to its higher bandwidth and the ability to further reduce external passive component size. Comparing with low frequency counterparts, high frequency switching converter design is more difficult in terms of the stability modeling, high switching loss and difficult current sensing etc. The objective of this dissertation is to study the design issues for monolithic integration of high frequency switching DC-DC converter. For this purpose, a high frequency, wide input range monolithic buck converter ASIC with fast transient response is designed based on advanced trench BCD technology. Stability is the fundamental requirement in designing switching converter ASIC. Achieving this requires an accurate loop gain design, especially for monolithically integrated high frequency switching converter since compensator is fixed on silicon and loop delay is comparable with switching cycle. Since DC-DC switching converters are time-varying system, traditional small signal analysis in SPICE cannot be directly used to simulate the loop gain of this kind of system. A periodic small signal analysis based method is proposed to analyze and simulate DC-DC switching converter inside a SPICE like simulator without the need for averaging. This general method is suitable for any switching regulators. The results are accurate comparing with average modeling and experiment results even at high frequency part. A general procedure to design loop gain is proposed. Several novel design concepts are proposed for monolithic integration of high frequency switching DC-DC converter; a novel control scheme-Cotangent Control (Ctg control) is proposed for fast transient response; In order to realize on-chip implementation of the compensator, especially for low frequency zero, active feedback compensator is developed and a general design procedure is proposed. Adaptive compensation concept is proposed to stabilize the whole system for a wide application range. Multi-stage driver and multi-section device concepts are investigated for high efficiency and low noise power stage design. And finally, a new noise insensitive lossless RC sensor is proposed for high speed current sensing. At the end of this dissertation, the test results of the fabricated chip are presented to verify the correctness of these design concepts. / Ph. D.

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more and more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM) is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. In the near future, VRM will be replaced with VRD because of the parasitic components effect. The specifications requirements for VRD are even more challenging than VRM. With this kind of tight tolerance, high current and fast current slew rate, transient response requirements for VRD design are very challenging, especially for step-down transient. During step-down transient, there is some additional energy stored in inductor. Traditional switching regulator like multi-phase buck can do nothing for this even by saturating the duty cycle to 0. All of the additional energy in inductor will be dumped into output cap and cause a large voltage spike at the output voltage. Even for step-up transient, traditional linear control like voltage loop control can't provide enough bandwidth because of the slow compensation and slow slew rate of the error amplifier. So the voltage drop is still quite large. Comparing with traditional linear controlled switching regulator such as voltage control and current control buck converter, active clamp has a lot of the advantages for the transient response. With proper design, active clamp can generate a very high bandwidth since there is no compensator needed in the control loop. Since active clamp bypasses inductor and is connected directly to the output cap, it can quickly source and sink current from the output cap even during the step-down transient and prevent overshooting of the output voltage. This is the biggest advantage for active clamp comparing with traditional linear control. In this thesis, a new active clamp structure is proposed. Several new concepts are proposed like non-linear Gm, built-in offset Gm, error signal feedback and AVP design. A one-channel buck converter with new active clamp and voltage loop control is implemented and verified using real transistors based on 0.5um CMOS process. / Master of Science

A total number of 849 tests were conducted to investigate the transient response of liquid injectors with various geometries including different taper angles, injection angles and orifice lengths. High-speed videos were analyzed to characterize refill times and back-flow distances of nine different injector geometries subjected to a ethylene-oxygen detonation wave. Water was used as the working fluid and experiments were performed at two different vessel pressure settings (60 and 100 psia). Although a minimal difference was found between plain and angled injectors due to having constant orifice diameter geometry, introduction of taper angle resulted in more agile injectors with less sensitivity to ambient and feed pressures. Several attempts were made to normalize refill times and obtain a general trend for transient response of liquid injectors.

"Hearing loss affects approximately 1 in 10 people in the world and this percentage is increasing every year. Some of the most common causes of hearing loss are disorders of the middle-ear. Early detection and diagnosis of hearing loss as well as research to understand the hearing processes depend on medical and research tools for quantification of hearing capabilities and the function of the middle-ear in the complex acousto-mechanical transformation of environmental sounds into vibrations of the middle-ear, particular of the human tympanic membrane (TM or eardrum). Current ear exams assess the state of a patient’s hearing capabilities mainly based on qualitative evaluation of the healthiness of the TM. Existing quantitative clinical methods for description of the motion of the TM are limited to either average acoustic estimates (admittance or reflectance) or single-point displacement measurements. Such methods could leave examiners and researchers blind to the complex spatio-temporal response of the nanometer scale displacements of the entire TM. Current state-of-the-art medical research tools provide full-field nanometer displacement measurements of the surface of the human TM excited by steady state (tonal) stimuli. However, to fully understand the mechanics of hearing, and the complex acousto-mechanical characteristics of TM in particular, new tools are needed for full-field high-speed characterization of the nanometer scale displacements of the human TM subjected to impulse (wideband) acoustic excitation. This Dissertation reports the development of a new high-speed holographic system (HHS) for full-field nanometer transient (i.e., > 10 kHz) displacement measurement of the human middle-ear and the tympanic membrane, in particular. The HHS allows spatial (i.e., >500k data points) and temporal (i.e., > 40 kHz) resolutions that enable the study of the acoustical and mechanical characteristics of the middle-ear at a level of detail that have never been reached before. The realization of the HHS includes the development and implementation of novel phase sampling and acquisition approaches that allow the use of state-of-the-art high-resolution (i.e., >5 MP) and high-speed (> 80,000 fps) cameras through modular and expandable control architectures. The development of novel acquisition approaches allows the use of conventional speed (i.e., <20 fps) cameras to realize high-temporal resolutions (i.e., <15 us) at equivalent sampling rates of > 50,000 fps with minimum hardware cost and modifications. The design and implementation of novel spatio-temporal phase sampling methods utilize the high temporal resolution (i.e., < 5 us exposure) and frame rate (i.e., >80,000 fps) of high-speed cameras without imposing constraints on their spatial resolution (i.e., >20 um pixel size). Additionally, the research and in-vivo applications capabilities of the HHS are extended through the development and implementation of a holographic otoscope head (OH) and a mechatronic otoscope positioner (MOP). The large (i.e., > 1 GB with > 8x10^9 parameters) spatio-temporal data sets of the HHS measurements are automatically processed by custom parallel data mining and interpretation (PDMI) methods, which allow automatic quantification of medically relevant motion parameters (MRMPs), such as modal frequencies, time constants, and acoustic delays. Such capabilities could allow inferring local material properties across the surface of the TM. The HHS is a new medical tool that enables otologists to improve the quality of diagnosis and treatments as well as provides researchers with spatio-temporal information of the hearing process at a level of detail never reached before. "