Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power consumption and limits for electromagnetic radiation are two of the main problems with handheld devices today and an efficient error correcting code will lower the transmission power and therefore also the power consumption of the device. Duo-binary CTC is an improvement of the innovative turbo codes presented in 1996 by Berrou and Glavieux and is in use in many of today's standards for radio communication i.e. IEEE 802.16 (WiMAX) and DVB-RSC. This report describes the development of a duo-binary CTC decoder and the different problems that were encountered during the process. These problems include different design issues and algorithm choices during the design. An implementation in VHDL has been written for Alteras Stratix II S90 FPGA and a reference-model has been made in Matlab. The model has been used to simulate bit error rates for different implementation alternatives and as bit-true reference for the hardware verification. The final result is a duo-binary CTC decoder compatible with Alteras Stratix II designs and a reference model that can be used when simulating the decoder alone or the whole signal processing chain. Some of the features of the hardware are that block sizes, puncture rates and number of iterations are dynamically configured between each block Before synthesis it is possible to choose how many decoders that will work in parallel and how many bits the soft input will be represented in. The circuit has been run in 100 MHz in the lab and that gives a throughput around 50Mbit with four decoders working in parallel. This report describes the implementation, including its development, background and future possibilities.

This thesis aims at providing results and insight towards the application of turbo-codes in digital communication systems, mainly in three parts. The first part considers systems of combined turbo-code and modulation. This section follows the pragmatic approach of the first proposed such system. It is shown that by optimizing the labeling method and/or modifying the puncturing pattern, improvements of more than 0. 5 dB insignal to noise ratio (SNR) are achieved at no extra cost of energy, complexity, or delay. Conventional turbo-codes with binary signaling divide the bit energy equally among the transmitted turbo-encoder output bits. The second part of this thesis proposes a turbo-code scheme with unequal power allocation to the encoder output bits. It is shown, both theoretically and by simulation, that by optimizing the power allocated to the systematic and parity check bits, improvements of around 0. 5 dB can be achieved over the conventional turbo-coding scheme. The third part of this thesis tackles the question of ``the sensitivity of the turbo-code performance towards the choice of the interleaver'', which was brought up since the early studies of these codes. This is the first theoretical approach taken towards this subject. The variance of the bound is evaluated. It is proven that the ratio of the standard deviation over the mean of the bound is asymptotically constant (for large interleaverlength, N), decreases with N, and increases with SNR. The distribution of the bound is also computationally developed. It is shown that as SNR increases, a very low percentage of the interleavers deviate quite significantly from the average bound but the majority of the random interleavers result in performances very close to the average. The contributions of input words of different weights in the variance of performance bound are also evaluated. Results show that these contributions vary significantly with SNR and N. These observations are important when developing interleaver design algorithms.

This dissertation deals with the design of bandwidth-efficient coding schemes with Low-Density Parity-Check (LDPC) for reliable wireless communications. Code design for wireless channels roughly falls into three categories: (1) when channel state information (CSI) is known only to the receiver (2) more practical case of partial CSI at the receiver when the channel has to be estimated (3) when CSI is known to the receiver as well as the transmitter. We consider coding schemes for all the above categories. For the first scenario, we describe a bandwidth efficient scheme which uses highorder constellations such as QAM over both AWGN as well as fading channels. We propose a simple design with LDPC codes which combines the good properties of Multi-level Coding (MLC) and bit-interleaved coded-modulation (BICM) schemes. Through simulations, we show that the proposed scheme performs better than MLC for short-medium lengths on AWGN and block-fading channels. For the first case, we also characterize the rate-diversity tradeoff of MIMO-OFDM and SISO-OFDM systems. We design optimal coding schemes which achieve this tradeoff when transmission is from a constrained constellation. Through simulations, we show that with a sub-optimal iterative decoder, the performance of this coding scheme is very close to the optimal limit for MIMO (flat quasi-static fading), MIMO-OFDM and SISO OFDM systems. For the second case, we design non-systematic Irregular Repeat Accumulate (IRA) codes, which are a special class of LDPC codes, for Inter-Symbol Interference (ISI) fading channels when CSI is estimated at the receiver. We use Orthogonal Frequency Division Multiplexing (OFDM) to convert the ISI fading channel into parallel flat fading subchannels. We use a simple receiver structure that performs iterative channel estimation and decoding and use non-systematic IRA codes that are optimized for this receiver. This combination is shown to perform very close to a receiver with perfect CSI and is also shown to be robust to change in the number of channel taps and Doppler. For the third case, we look at bandwidth efficient schemes for fading channels that perform close to capacity when the channel state information is known at the transmitter as well as the receiver. Schemes that achieve capacity with a Gaussian codebook for the above system are already known but not for constrained constellations. We derive the near-optimum scheme to achieve capacity with constrained constellations and then propose coding schemes which perform close to capacity. Through linear transformations, a MIMO system can be converted into non-interfering parallel subchannels and we further extend the proposed coding schemes to the MIMO case too.

The use of multiple antennas at the transmitter and/or the receiver promises greatly increased capacity. This can be useful to meet the ever growing demand of wireless connectivity, provided we can find techniques to efficiently exploit the advantages of the Multiple-Input Multiple-Output (MIMO) system. This work explores the MIMO system in a flat quasi-static fading scenario. Such a channel occurs, for example, in packet data systems, where the channel fade is constant for the duration of a codeword and changes independently from one transmission to another. We first show why it is hard to compute the true constrained modulation outage capacity. As an alternative, we present achievable lower bounds to this capacity based on existing space-time codes. The bounds we compute are the fundamental limits to the performance of these space-time codes under maximum-likelihood decoding, optimal outer codes and asymptotically long lengths. These bounds also indicate that MIMO systems have different behavior under Gaussian signaling (unconstrained input) and under the finite alphabet setting. Our results naturally suggest the use of concatenated codes to approach near-capacity performance. However, we show that a system utilizing an iterative decoder has a fundamental limit – it cannot be universal and therefore it cannot perform arbitrarily close to its outage limit. Next, we propose two different transceiver structures that have good performance. The first structure is based on a novel BCJR-decision feedback decoder which results in performance within a dB of the outage limit. The second structure is based on recursive realizations of space-time trellis codes and uses iterative decoding at the receiver. This recursive structure has impressive performance even when the channel has time diversity. Thus, it forms the basis of a very flexible and robust MIMO transceiver structure.

Turbo codes have been the subject of much research in recent years, producing results very close to the theoretical limit set by Shannon. The codes have been successfully implemented in satellite and video conferencing systems and provision has been made in 3rd generation mobile systems. These codes have not been used for short frame systems due to the delay at the decoder. In this thesis, comprehensive comparisons of the two common decoding algorithms are made, with reference to short frames. The effects of increasing memory size of component codes, frame sizes, utilising puncturing and errors in channel estimation are investigated over AWGN and Rayleigh fading channels. The decoder systems are compared for complexity as well as for equal numbers of iterations. Results show that less complex decoder strategies produce good results for voice quality bit error rates. Investigations are also made into the effects of errors in signal-to-noise ratio estimation at the SOVA turbo decoder, showing this decoding algorithm to be more resilient than Log-MAP decoders in published literature. The decoders are also tested over channels displaying inter-symbol interference. Channels include a time-invariant channel and three ETSI standard time-varying channels simulating indoor, pedestrian and vehicular situations, upgraded for more realistic Doppler effect. To combat these types of channels, a derivative of turbo codes, turbo equalisation is often used. To keep receiver delay to a minimum, decision feedback equalisation is used here. Results show that the combination can produce improvements in decoded results with increasing turbo iterations where ISI is low, but that iterative improvements do not occur under harsh circumstances. The combination produces much superior results compared with codes on their own under even the most extreme circumstances.

Error correction codes are a means of including redundancy in a stream of information bits to allow the detection and correction of symbol errors during transmission. The birth of error correction coding showed that Shannon's channel capacity could be achieved when transmitting information through a noisy channel. Turbo codes are a very powerful form of error correction codes that bring the performance of practical coding even closer to Shannon's theoretical specifications. Bit-error-rate (BER) performance and power dissipation are two important measures of performance used to characterize communication systems. Subject to the law of diminishing returns, as the resolution of the analog-to-digital converter (ADC) in the decoder increases, BER improves, but power dissipation increases. The number of decoding iterations has a similar effect on the BER performance and power dissipation of turbo coded systems. This is significant since turbo decoding is typically practiced in a fixed iterative manner, where all transmitted frames go through the same number of iterations. This is not always necessary since certain "good" frames would converge to their final bits within a few iterations, and other "bad" frames never do converge. In this thesis, we investigate the technical feasibility of adapting the resolution of the ADC in the decoder, and the number of decoding iterations, in order to obtain the best trade-off possible between BER performance and power dissipation in a communication system. With the aid of computer-aided simulations, this thesis investigates the performance and practical implementation issues associated with incorporating a variable resolution ADC into the decoder structure of turbo codes. The possibility of further power conservation resulting from reduced decoding computation is also investigated with the use of a recently developed iterative stopping criterion. / Master of Science

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One recent method to approach the capacity of a channel is Turbo Coding. However, a major concern with the implementation of a Turbo Code is the overall complexity and real-time throughput of the digital hardware system. The salient design problem of Turbo Coding is the iterative decoder, which must perform calculations over all possible states of the trellis. Complex computations such as exponentiations, logarithms and division are explored as part of this research to compare the complexity of the traditionally avoided maximum a-posteriori probability (MAP) decoder to that of the more widely accepted and simplified Logarithm based MAP decoder (LOG-MAP). This research considers the fine grained implementation and processing of MAP, LOG-MAP and a hybrid LOG-MAP-Log Likelihood Ratio (LLR) based Turbo Codes on a Xilinx Virtex 4 PGA. Verification of the Turbo Coding system performance is demonstrated on a Xilinx Virtex 4 ML402SX evaluation board with the EDA of the Xilinx System Generator utilizing hardware co-simulation. System throughput and bit error rate (BER) are the performance metrics that are evaluated as part of this research. An efficient system throughput is predicated by the parallel design of the decoder and BER is determined by data frame size, data word length and the number of decoding iterations. Furthermore, traditional and innovative stopping rules are evaluated as part of this research to facilitate the number of iterations required during decoding. / Engineering