With sub-micron silicon processing technology reaching under 30nm, it becomes more difficult for integrated circuits to achieve higher integration through the scaling down of the transistor size. Three-dimensional integrated circuit (3D-IC) technology stacks multiple dies together and connects them using through-silicon vias (TSVs). This is a low cost and highly efficient way to increase integration. TSVs and stacked dies are two major features of the 3D-IC technology. However, the stacked structures using TSV interconnects induce concerns in reliability such as TSV strain effect, heat problem, and TSV coupling at high frequency, etc. The reliability concerns need to be carefully addressed before 3D-IC technologies can be widely adopted by the industry. Many studies have been carried out in this field, but there has not been much significant work done for testing electrical, mechanical and thermal issues of the 3D-IC technology simultaneously on a single test chip. In this work, a test chip including various test structures was designed to study and analyze these issues in a 3D-IC technology. An accurate resistance and capacitance (RC) model of the TSV for low frequency design was developed, high frequency electrical performance of the TSVs was characterized, coupling between TSVs was modeled, and the stress effect and the heat dissipation method were analyzed in the 3D-IC technology. The TSV model could be added to the design kit for future 3D-IC design and other results could be used to improve the reliability of 3D-IC designs and optimize the performance.

Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces large thermal mismatch stress in 3D-IC structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. TSV-induced stress effects on electron/hole mobility and device performance will be studied for the widely used 6-transistor (6T) SRAM cell. Simulation results in this study show that static noise margin (SNM), Read Margin (RM) and write margin (WM) tend to increase with decreasing electron mobility or increasing hole mobility. Considering TSV-induced stress, we propose that for practical layouts of TSV-based 3D-IC, p-type substrates should be placed further away from TSVs or closer to the smaller TSVs if multiple TSVs exist. / text

3D stacked ICs (3D-SICs) with multiple dies interconnected by through-silicon-vias(TSVs) are considered as a technology driver and proven to have overwhelming advantagesover traditional ICs with a single die in a package in terms of performance, powerconsumption and silicon overhead. However, these “super chips” bring new challengesto the process of IC manufacturing; among which, testing 3D-SICs is the major andmost complex issue to deal with. In traditional ICs, tests can usually be performedat two stages (test instances), namely: a wafer sort and a package test. Whereas for3D-SICs, tests can be performed after each stacking event where a new die is stackedover a partial stack. This expands the set of available test instances. A combination ofselected test instances where a test is performed (active test instance) is known as a testflow. Test time is a major contributor to the total test cost. Test time changes with theselected test flow. Therefore, choosing a cost effective test flow which will minimizesthe test time is absolutely essential.This thesis focuses on finding an optimal test flow which minimizes the test timefor a given 3D-SIC. A mathematical model has been developed to evaluate the test timeof any test flow. Then a heuristic has been proposed for finding a near optimal test flowwhich minimizes the test time. The performance of this approach in terms of computationtime and efficiency has been compared against the minimum test time obtainedby exhaustive search. The heuristic gives good results compared to exhaustive searchwith much lesser computation time.

<p>Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.</p><p>Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.</p><p>Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.</p><p>Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.</p><p>In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.</p><p>Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. In addition, the proposed on-chip debug circuitry can identify erroneous segments of observed data by using compact signatures that are stored in the DRAM a priori. Only failing intervals are off-loaded from a temporary trace buffer into DRAM, allowing for a more efficient use of the memory, resulting in a larger observation window.</p><p>In summary, this dissertation provides solutions to several challenges related to 3D test and debug that need to be addressed before volume manufacturing of 3D ICs can be viable.</p> / Dissertation

Dans cette thèse, nous étudions les architectures 3D NoC grâce à des implémentations de conception physiques en utilisant la technologie 3D réel mis en oeuvre dans l'industrie. Sur la base des listes d'interconnexions en déroute, nous procédons à l'analyse des performances d'évaluer le bénéfice de l'architecture 3D par rapport à sa mise en oeuvre 2D. Sur la base du flot de conception 3D proposé en se concentrant sur la vérification temporelle tirant parti de l'avantage du retard négligeable de la structure de microbilles pour les connexions verticales, nous avons mené techniques de partitionnement de NoC 3D basé sur l'architecture MPSoC y compris empilement homogène et hétérogène en utilisant Tezzaron 3D IC technlogy. Conception et mise en oeuvre de compromis dans les deux méthodes de partitionnement est étudiée pour avoir un meilleur aperçu sur l'architecture 3D de sorte qu'il peut être exploitée pour des performances optimales. En utilisant l'approche 3D homogène empilage, NoC topologies est explorée afin d'identifier la meilleure topologie entre la topologie 2D et 3D pour la mise en œuvre MPSoC 3D sous l'hypothèse que les chemins critiques est fondée sur les liens inter-routeur. Les explorations architecturales ont également examiné les différentes technologies de traitement. mettant en évidence l'effet de la technologie des procédés à la performance d'architecture 3D en particulier pour l'interconnexion dominant du design. En outre, nous avons effectué hétérogène 3D d'empilage pour la mise en oeuvre MPSoC avec l'approche GALS de style et présenté plusieurs analyses de conception physiques connexes concernant la conception 3D et la mise en œuvre MPSoC utilisant des outils de CAO 2D. Une analyse plus approfondie de l'effet microbilles pas à la performance de l'architecture 3D à l'aide face-à-face d'empilement est également signalé l'identification des problèmes et des limitations à prendre en considération pendant le processus de conception. / In this thesis, we study the exploration 3D NoC architectures through physical design implementations using real 3D technology used in the industry. Based on the proposed 3D design flow focusing on timing verification by leveraging the benefit of negligible delay of microbumps structure for vertical connections, we have conducted partitioning techniques for 3D NoC-based MPSoC architecture including homogeneous and heterogeneous stacking using Tezzaron 3D IC technlogy. Design and implementation trade-off in both partitioning methods is investigated to have better insight about 3D architecture so that it can be exploited for optimal performance. Using homogeneous 3D stacking approach, NoC architectures are explored to identify the best topology between 2D and 3D topology for 3D MPSoC implementation. The architectural explorations have also considered different process technologies highlighting the wire delay effect to the 3D architecture performance especially for interconnect-dominated design. Additionally, we performed heterogeneous 3D stacking of NoC-based MPSoC implementation with GALS style approach and presented several physical designs related analyses regarding 3D MPSoC design and implementation using 2D EDA tools. Finally we conducted an exploration of 2D EDA tool on different 3D architecture to evaluate the impact of 2D EDA tools on the 3D architecture performance. Since there is no commercialize 3D design tool until now, the experiment is important on the basis that designing 3D architecture using 2D EDA tools does not have a strong and direct impact to the 3D architecture performance mainly because the tools is dedicated for 2D architecture design.

The main objective of this research is to examine the performance, power noise, and thermal trade-offs in modern traditional (2D) and three-dimensionally-integrated (3D) architectures and to present design automation tools and physical design methodologies that enable higher reliability while maintaining microarchitectural performance for these systems. Five main research topics that support this goal are included. The first topic focuses on thermal reliability. The second, third, and fourth, topics examine power-supply noise. The final topic presents a set of physical design and analysis methodologies used to produce a 3D design that was sent for fabrication in March of 2010. The first section of this dissertation details a microarchitectural floorplanning algorithm that enables the user to choose and adjust the trade-off between microarchitectural performance and general operating temperature in both 2D and 3D systems, which is a major determinant of overall reliability and chip lifetime. Simulation results demonstrate that the algorithm performs as expected and successfully provides the user with the desired trade-off. The first section also presents a thermal-aware microarchitectural floorplanning algorithm designed to help reduce the operating temperature of the cores in the unique environment present within multi-core processors. Heat-coupling between neighboring cores is considered during the optimization process to provide floorplans that result in lower maximum temperature. The second section explores power-supply noise in processors caused by fine-grained clock-gating and describes a floorplanning algorithm created to work with an active noise-canceling clock-gating controller. Simulation results show that combining these two techniques results in lower power-supply noise with minimal processor performance impact. The third section turns to future 3D systems with a large number of stacked active layers (many-tier systems) and examines power-supply delivery challenges in these systems. Parasitic resistance, capacitance, and inductance are calculated for the 3D vias, and the results of scaling various parameters in the power-supply-network design are presented. Several techniques for reducing power-supply-network noise in these many-tier systems are explored. The fourth section describes a layout-level analysis of a novel power distribution through-silicon-via topology and it's effect on IR-drop and dynamic noise. Simulations show that both types of power-supply noise can be reduced by more than 20\% in systems with non-uniform per-tier power dissipation when using the proposed topology. The final section explains the physical design and analysis techniques used to produce the layouts for 3D-MAPS, a 64-core 3D-stacked memory-on-processor system targeted at demonstration of large memory bandwidth using 3D connections. The 3D-aware physical design flow utilizing non-3D-aware commercial tools is detailed, along with the techniques and add-ons that were developed to enable this process.

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.

With the reduction in transistor dimensions to a few tens of nanometers as a result of aggressive scaling, interconnect delay has now become one of the major bottlenecks to chip performance. Secondly, interconnect power and area have both become a significant part of the total chip power and area respectively. These concerns have led to an effort to find a solution that would reduce interconnect delay and leakage, while also reducing the area they occupy in a chip, so that either the chip area could be reduced, or more functionality could be incorporated within a certain area. 3D integration, i.e., stacking of various sub-systems of a chip on top of each other, enables chip-makers to achieve higher packaging efficiencies, thereby reducing system cost, while also reducing delay (and thus increasing the available bandwidth). Through Silicon Vias (TSVs) have emerged as the key interconnect technology for 3D ICs, as they enable significant reduction in delay and leakage compared to wire-bonded dies, while also occupying less area in a package. They also enable stacking of sub-systems which differ in functionality, and stacking of multiple dies. Also, unlike wire-bond, dies need not be bandwidth limited by the number of wire bonds that can be made between two levels in a stack. While TSVs offer many advantages, one of the concerns when implementing a 3D system using TSVs is the mechanisms of interaction between a TSV and a device in its vicinity. Another concern is with regards to the interaction between the TSV and its surrounding material. The purpose of this thesis is to develop a TCAD framework for process and device co-simulation of a TSV transistor system to study the various mechanisms of interaction between them, as well as between the TSV and substrate. The utility of this tool has been demonstrated by studying two mechanisms of interaction, the effect of TSV-induced stress, and the effect of TSV-device electrical coupling, on the electrical performance of bulk NMOS and PMOS transistors. The results from 3D TCAD simulations suggest that designers can scale the keep out zone (KOZ) around TSVs more aggressively, allowing for more efficient utilization of silicon area, without a drastic performance penalty.

3D-NoC architectures are the amalgamation of the 3D integration (Die stacking of 3D-IC Technology) with the increased scalability found in NoC. Originally, it was proposed to tackle the problem of increasing the number of cores in the 2D plane which seems incompetent due to long distance interconnects. This architecture is aimed to optimize performance, power consumption, achieve low latency and increase the network bandwidth. Nevertheless, as more dies were being stacked vertically, IC operating frequency increases and this leads to some thermal issues which include high power density which increases average temperature. In addition to that, longer heat dissipation path results in different heat dissipation in each layer of the NoC which worsen the situation. An increase in the overall power consumption increases the average temperature, reduces performance and reliability. In this paper, an adaptive thermal-aware management scheme was proposed for 3D-NoCs, concentrating more on the hotspot regions in the network. This proposed protocol employs the thermal state of intermediate nodes and flits properties in a random uniform distributive way for packet routing. The proposed algorithm increases network availability and tends to distribute the temperature of the system evenly and uniformly within the network and making sure that packets are not forwarded to the hotspot node(s) and only flits with certain properties in the distribution are forwarded to the hotspot node(s). Before or during transmission, these two distributions must be calculated alongside the current node temperature to knowing which state of the distribution that node and flit belong to. The simulation shows this gave better performance in throughput and reliability of the network by reducing the number of hotspot nodes in the NoC. The proposed algorithm also reduces power consumption which is a function of temperature. Simulations show that our proposed algorithm reduces the total power/energy consumed by more than 59\% and throughput is improved by 69\% compared to a traditional XYZ routing. / Graduate

This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C. To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer. / Master of Science