Double Chooz (DC) est une expérience d'oscillation de neutrinos auprès de réacteurs, dont la finalité est la mesure du dernier angle de mélange encore inconnu θ13 . Elle hérite de l'expérience passée CHOOZ qui était limitée par des erreurs statistiques et systématiques à un niveau similaire d'environ 2.8%. Afin de diminuer l'erreur statistique, la masse de la cible du détecteur DC a été augmentée tandis que la réduction de l'erreur systématique est assurée par l'utilisation de deux détecteurs identiques. Un détecteur sera situé dans le voisinage des coeurs des réacteurs dans le but de contrôler le flux et le spectre des anti-νe émis alors que l'autre sera placé à l'endroit où l'effet d'oscillation maximal est attendu. Le premier est communément dénommé 'détecteur proche' par opposition au second dénommé 'd ́etecteur lointain'. Les erreurs attendues sont 0.5% (stat.) et 0.6% (syst.) pour une ultime mesure sin2 2θ13 = 0.05 (θ13 = 6.5◦ ) à trois écart-type après trois années de prise de données. Le démarrage du détecteur lointain est attendu pour novembre 2010 tandis que le détecteur proche sera opérationnel pour la mi-2012. Cette thèse présente tout d'abord une contribution matérielle à l'expérience avec le test des Flash-ADCs qui constituent le coeur du système d'acquisition. Ensuite, elle présente des analyses effectuées sur des simulations Monte Carlo afin d'optimiser la conception du détecteur. Ce travail était composé d'analyses dans le but de choisir des composantes du détecteur avec la contamination radioactives qui convient, des analyses dans le but d'obtenir la meilleure résolution en énergie possible et une manière de déclencher la sauvegarde des données par le système d'acquisition la plus stable et la plus robuste possible. Les travaux sur l'optimisation du détecteur et les connaissances acquises sur les Flash-ADCs nous ont amené à envisager une nouvelle reconstruction spatiale basée sur le temps de vol des photons. Toutes ces contributions à l'expérience sont présentées en détails à travers ce manuscrit.

Thesis (MScEng)--Stellenbosch University, 2014. / ENGLISH ABSTRACT: With CubeSats becoming popular as a cheap alternative to larger satellites, the need for advanced miniature attitude determination and control systems (ADCS) arises to meet the pointing requirements of satellite operations such as earth imaging and orbit maintenance. This thesis describes the design of a complete ADCS for use on CubeSats. A previously designed CubeSat on-board-computer, CubeComputer, and ne sun and nadir sensor, CubeSense, is incorporated in the design. The remaining requirements with regard to sensors and actuators were met by CubeControl, an additional module, the design, manufacturing and testing of which are described. CubeControl can implement magnetic control with the use of a magnetometer and three magnetorquers. It is also capable of driving three reaction wheels for accurate active 3-axis stabilization. / AFRIKAANSE OPSOMMING: Met CubeSats wat gewild raak as 'n goedkoop alternatief tot groter satelliete ontstaan die behoefte vir gevorderde miniatuur ori entasiebepaling en -beheerstelsels wat satelliet operasies soos aardwaarneming en wentelbaan korreksies moontlik maak. Hierdie tesis beskryf die ontwerp van 'n volledige ori entasiebepaling en -beheerstelsel vir CubeSats. 'n Voorheen ontwikkelde CubeSat aanboordrekenaar, CubeComputer, en 'n fyn sonsensor en nadirsensor, CubeSense, is ingesluit in die ontwerp. Die orige benodighede met verband tot sensors en aktueerders word vervul deur CubeControl, 'n addisionele module waarvan die ontwerp, vervaardiging en toetsing beskyf word. CubeControl kan magnetiese beheer implementeer deur gebruik te maak van 'n magnetometer en drie magneetstange. Dit kan ook drie reaksiewiele aandryf vir akkurate aktiewe 3-as stabilisering.

This thesis aims to design a reliable CubeSat platform, including the avionic subsystems that can sustain a high radiation environment for a mission having a lifetime of at least six months. The science instruments put stringent requirements on the platform to achieve and maintain the desired spin rate. The simulation background is set up in Systems Tool Kit (STK). A trade-off analysis for the Attitude and Orbit Control System (AOCS) of FORESAIL 2 was done, focusing on the actuators and their ability to offer the right amount of torque to fulfill the tether deployment. Mission design analyses were performed to conclude on the form factor of the CubeSat, its ability to generate power, its compliance with the Space Debris Mitigation (SDM) technical requirements, and the total radiation dose accumulated. It was found that a 6U form factor is preferred to allocate more space for each subsystem, alongside with generating enough power for the satellite to work in all modes wanted. The mission is compliant with European Cooperation for Space Standardization (ECSS) and International Organization for Standardization (ISO) standards if the CubeSat is to be launched in September 2022. To allow a threshold limit of 10 krads on the components of the satellite, a shielding wall of 7 mm should be implemented on the CubeSat’s structure. Major requirements for the designed mission were written to initialize the investigation on the sensors and actuators. The results showed that only a propulsion system provided the necessary angular momentum to deploy the tether. The lack of magnetic field makes magnetorquers almost unusable in the desired orbit, leaving reaction wheels as the only option remaining to assist the propulsion units. The different analyses and simulations led to a final AOCS configuration composed of five various sensors (Sun sensors, magnetometers, a GPS, an IMU, and housekeeping sensors) for the attitude determination. A propulsion system and reaction wheels will provide the necessary control over the satellite.

Attitude Determination and Control System (ADCS) is often a complex system on-board any  satellite  which  needs  validation  and  testing  to  prove  its  operability  and  verify  its software  compatibility  with  hardware  and  other  subsystems.    One  failure  in  orbit  is extremely expensive in terms of cost and time due to payload preparation and launch. The ideal test bench would be the one that perfectly simulates the space environment and all its main factors such as weightlessness, Earth’s Magnetic Field (EMF), vacuum, neutral particles, plasma and radiation, among others.  The target in this case was the Earth’s Magnetic Field (EMF), solved with a Helmholtz Cage in a Merritt Configuration, and weightlessness, not implemented but analysed in detail where different alternatives are proposed, similar to market solutions.As  derived  from  literature  and  simulations  executed  along  this  M.  Sc.    Thesis,  the Merritt Cage seems beneficial against any other configuration in terms of magnetic field uniformity and effective volume.  After the design and assembly of the test bench, both properties were verified and successfully achieved, despite the lack of calibration, not executed because of time limitation, and tiny issues encountered along the full evolutionof the project. / Attitude Determination and Control System (ADCS) är ofta ett komplicerat system ombord på alla satelliter som behöver validering och testning för att bevisa dess användbarhet och  verifiera dess  programvarukompatibilitet med  hårdvara och  andra delsystem.   Ett fel  i  omloppsbana  är  extremt  dyrt  med  avseende  på  kostnader  och  tid  på  grund  av förberedelse  och  lansering  av  nyttolast  Den  ideala  testbänken  skulle  vara  den  som perfekt  simulerar  rymdmiljön  och  alla  dess  huvudfaktorer  såsom  viktlöshet,  Earth’s Magnetic  Field  (EMF),  vakuum,  neutrala  partiklar,  plasma  och  strålning,  bland  andra. Målet  i  detta  fall  var  EMF,  löst  med  en  Helmholtz-bur  i  en  Merritt-konfiguration,  och viktlöshet,  inte  implementerad  men  analyserad  i  detalj  där  olika  alternativ  föreslås, liknande marknadslösningar.Som härstammar från litteratur och simuleringar utförda längs denna M. Sc. Avhandling verkar Merritt Cage vara gynnsam mot annan konfiguration när det gäller magnetfältens enhetlighet och effektiv volym.  Efter konstruktionen och montering av testbänken, var båda egenskaperna verifierade och framgångsrikt uppnådda, trots bristen på kalibrering, inte  genomförda  på  grund  av  tidsbegränsning,  och  små  problem  som  uppstod  underprojektets fulla utveckling.

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: The Electronic Systems Laboratory at Stellenbosch University is currently developing a fully 3-axis controlled Attitude Determination and Control Subsystem (ADCS) for CubeSats. This thesis describes the design and development of an Onboard Computer (OBC) suitable for ADCS application. A separate dedicated OBC for ADCS purposes allows the main CubeSat OBC to focus only on command and data handling, communication and payload management. This thesis describes, in detail the development process of the OBC. Multiple Microcontroller Unit (MCU) architectures were considered before selecting an ARM Cortex-M3 processor due to its performance, power efficiency and functionality. The hardware was designed to be as robust as possible, because radiation tolerant and redundant components could not be included, due to their high cost and the technical constraints of a CubeSat. The software was developed to improve recovery from lockouts or component failures and to enable the operational modes to be configured in real-time or uploaded from the ground station. Ground tests indicated that the OBC can handle radiation-related problems such as latchups and bit-flips. The peak power consumption is around 500 mW and the orbital average is substantially lower. The proposed OBC is therefore not only sufficient in its intended application as an ADCS OBC, but could also stand in as a backup for the main OBC in case of an emergency. / AFRIKAANSE OPSOMMING: Die Elektroniese Stelsels Laboratorium by die Universiteit van Stellenbosch is tans besig om ’n volkome 3-as gestabiliseerde oriëntasiebepaling en -beheerstelsel (Engels: ADCS) vir ’n CubeSat te ontwikkel. Hierdie tesis beskryf die ontwerp en ontwikkeling van ’n aanboordrekenaar (Engels: OBC) wat gebruik kan word in ’n ADCS. ’n Afsonderlike OBC wat aan die ADCS toegewy is, stel die hoof-OBC in staat om te fokus op beheer- en datahantering, kommunikasie en loonvragbestuur. Hierdie tesis beskryf breedvoerig die werkswyse waarvolgens die OBC ontwikkel is. Verskeie mikroverwerkers is as moontlike kandidate ondersoek voor daar op ’n ARM Cortex-M3-gebaseerde mikroverwerker besluit is. Hierdie mikroverwerker is gekies vanweë sy spoed, effektiewe kragverbruik en funksionaliteit. Die hardeware is ontwikkel om so robuust moontlik te wees, omdat stralingbestande en oortollige komponente weens kostebeperkings, asook tegniese beperkings van ’n CubeSat, nie ingesluit kon word nie. Die programmatuur is ontwikkel om van ’n uitsluiting en ’n komponentfout te kan herstel. Verder kan programme wat tydens vlug in werking is, verstel word en vanaf ’n grondstasie gelaai word. Grondtoetse het aangedui dat die OBC stralingverwante probleme, soos ’n vergrendeling (latchup) of bis-omkering (bit-flip), kan hanteer. Die maksimum kragverbruik is ongeveer 500 mW en die gemiddelde wentelbaankragverbruik is beduidend kleiner. Die voorgestelde OBC is dus voldoende as ADCS OBC asook hoof-OBC in geval van nood.

abstract: This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW power. Another example achieves 78.2dB SNR in 31.25µs measurement time and consumes 63µW power. The second ADC architecture is a multi-mode, dynamically zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)- independent, dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW power consumption from a 1.2 V supply. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011

In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in most digital signal processing (DSP) systems and are, for example, used for interpolation and decimation. A typical application for the filters considered in this work is mobile communication systems, where high throughput and low power consumption are required. In the first part of the thesis we discuss implementation of high throughput lattice wave digital filters (LWDFs). Here arithmetic transformation of first- and second-order Richards’ allpass sections are proposed. The transformations reduces the iteration period bound of the filter realization, which can be used to increase the throughput or reduce the power consumption through power supply voltage scaling. Implementation of LWDFs using redundant, carry-save arithmetic is considered and the proposed arithmetic transformations are evaluated with respect to throughput and area requirements. In the second part of the thesis we discuss three case studies of implementations of digital filters for typical applications with requirements on high throughput and low power consumption. The first involves the design and implementation of a digital down converter (DDC) for a multiple antenna element radar receiver. The DDC is used to convert a real IF input signal into a complex baseband signal composed of an inphase and a quadrature component. The DDC includes bandpass sampling, digital I/Q demodulation, decimation, and filtering and three different DDC realizations are proposed and evaluated. The second case study is a combined interpolator and decimator filter for use in an OFDM system. The analog-to-digital converters (ADCs) and the digital-to-analog converters (DACs) work at a sample rate twice as high as the Nyquist rate. Hence, interpolation and decimation by a factor of two is required. Also, some channel shaping is performed which complicates the filter design as well as the implementation. Frequency masking techniques and novel filter structures was used for the implementation. The combined interpolator and decimator was successfully implemented using an LWDF in a 0.35 mm CMOS process using carry-save arithmetic. The third case study is the implementation of a high-speed decimation filter for a SD ADC. The decimator has an input data rate of 16 Gsample/s and the decimation factor is 128. The decimation is performed using two cascaded digital filters, a comb filter followed by a linear-phase FIR filter. A novel hardware structure for single-bit input digital filters is proposed. The proposed structure was found to be competitive and was used for the implementation. The decimator filter was successfully implemented in a 0.18 mm CMOS process using standard cells. In the third part of the thesis we discuss efficient realization of sum-of-products and multiple-constant multiplications that are used in, for example, FIR filters. We propose several new difference methods that result in realizations with a low number of adders. The proposed design methods have low complexity, i.e., they can be included in the search for quantized filter coefficients.

Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented. / Graduation date: 2009

University of Macau / Faculty of Science and Technology / Department of Electrical and Electronics Engineering