A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

Submitted by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:21Z No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:37Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Approved for entry into archive by Divisão de Documentação/BC Biblioteca Central (ddbc@ufam.edu.br) on 2016-11-25T15:39:56Z (GMT) No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) / Made available in DSpace on 2016-11-25T15:39:56Z (GMT). No. of bitstreams: 1 Dissertação - Ewerton G. Oliveira.pdf: 6135162 bytes, checksum: 3a074865f59774e056e5a06dd0c49501 (MD5) Previous issue date: 2016-04-18 / This work presents a study on the behavior and effectiveness of different Fixed-Pattern Noise (FPN) reduction techniques applied to different pixel topologies operating in logarithmic mode. The purpose of such study is the establishment of a consistent way to perform fair cross comparison of the effectiveness of different FPN attenuation techniques applied to pixels with different topologies and designed in the same technological node, and thus establish judgment criteria for determining which topology will be most suitable for implementation of an image sensor operating in logarithimic mode. Investigations of the effectiveness of two similar FPN reduction techniques applied to four different pixel topologies were performed through Monte Carlo simulations. The analyses of results of output signal swing, total and residual FPN, signal-to-distortion ratio, power consumption and fill factor are able to demonstrate which pixel topologies yield better results in each of these criteria. Such results provide valuable data that allows a more concise decision on which pixel topology and FPN reduction technique to choose in the design of an imager array with wide dynamic range. / Este trabalho apresenta um estudo sobre o comportamento e eficácia de diferentes técnicas de redução de ruído de padrão fixo, do inglês fixed-pattern noise (FPN), aplicadas a diferentes topologias de pixel operando em modo logarítmico. A finalidade deste estudo é o estabelecimento de um meio consistente para realizar comparação cruzada imparcial da eficácia de diferentes técnicas de redução de FPN aplicadas a pixeis com diferentes topologias e projetados sob o mesmo rótulo tecnológico, e assim estabelecer critérios de julgamento que permitam determinar qual topologia será a mais adequada para implementação de um sensor de imagem operando em modo logarítmico. Investigações da eficácia de duas técnicas de redução de FPN similares aplicadas a quatro diferentes topologias de pixel foram realizadas através de simulações Monte Carlo. As análises dos resultados de excursão do sinal de saída, FPN total e residual, razão de distorção do sinal, consumo de energia e fator de preenchimento são capazes de demonstrar que topologias de pixel produzem melhores resultados em cada um destes critérios. Tais resultados proporcionam dados valiosos que permitem uma mais concisa decisão sobre qual topologia de pixel e técnica de redução de FPN escolher no projeto de um sensor de imagem com largo alcance dinâmico.

For the X-ray astronomy project Advanced Telescope for High ENergy Astrophysics (Athena) wafer-scale DEpleted P-channel Field Effect Transistor (DEPFET) detectors are proposed as Focal Plane Array (FPA) for the Wide Field Imager (WFI). Prototype structures with different pixel layouts, each consisting of 64 x 64 pixels, were fabricated to study four different DEPFET designs. This thesis reports on the results of the electrical and spectroscopic characterization of the different DEPFET designs. With the electrical qualification measurements the transistor properties of the DEPFET structures are investigated in order to determine whether the design intentions are reflected in the transistor characteristics. In addition, yield and homogeneity of the prototypes can be studied on die, wafer and batch level for further improvement of the production technology with regard to wafer-scale devices. These electrical characterization measurements prove to be a reliable tool to preselect the best detector dies for further integration into full detector systems. The spectroscopic measurements test the dynamic behavior of the designs as well as their spectroscopic performance. In addition, it is revealed how the transistor behavior translates into the detector performance. This thesis, as the first systematic study of different DEPFET designs on die and detector level, shows the limitations of the current DEPFET assessment methods. Thus, it suggests a new concise characterization procedure for DEPFET detectors as well as guidelines for expanded testing in order to increase the general knowledge of the DEPFET. With this study of four different DEPFET variants not only designs suitable for Athena mission have been found but also improvement impulses for the starting wafer-scale device production are provided.

For the X-ray astronomy project Advanced Telescope for High ENergy Astrophysics (Athena) wafer-scale DEpleted P-channel Field Effect Transistor (DEPFET) detectors are proposed as Focal Plane Array (FPA) for the Wide Field Imager (WFI). Prototype structures with different pixel layouts, each consisting of 64 x 64 pixels, were fabricated to study four different DEPFET designs. This thesis reports on the results of the electrical and spectroscopic characterization of the different DEPFET designs. With the electrical qualification measurements the transistor properties of the DEPFET structures are investigated in order to determine whether the design intentions are reflected in the transistor characteristics. In addition, yield and homogeneity of the prototypes can be studied on die, wafer and batch level for further improvement of the production technology with regard to wafer-scale devices. These electrical characterization measurements prove to be a reliable tool to preselect the best detector dies for further integration into full detector systems. The spectroscopic measurements test the dynamic behavior of the designs as well as their spectroscopic performance. In addition, it is revealed how the transistor behavior translates into the detector performance. This thesis, as the first systematic study of different DEPFET designs on die and detector level, shows the limitations of the current DEPFET assessment methods. Thus, it suggests a new concise characterization procedure for DEPFET detectors as well as guidelines for expanded testing in order to increase the general knowledge of the DEPFET. With this study of four different DEPFET variants not only designs suitable for Athena mission have been found but also improvement impulses for the starting wafer-scale device production are provided.