La théorie de l'échantillonnage uniforme des signaux, développée en particulier par C. Shannon, est à l'origine du traitement numérique du signal. Depuis, de nombreux travaux ont été consacrés à l'échantillonnage non uniforme. Celui-ci permet, d'une part, de modéliser les imperfections des dispositifs d'échantillonnage uniforme. D'autre part, l'échantillonnage peut être effectué de manière délibérément non uniforme afin de bénéficier de propriétés particulières, notamment un assouplissement des conditions portant sur le choix de la fréquence moyenne d'échantillonnage. La plupart de ces travaux reste dans un cadre théorique en adoptant des schémas d'échantillonnage et des modèles de signaux simplifiés. Or, actuellement, dans de nombreux domaines d'application, tels que les communications par satellites, la conversion analogique-numérique s'effectue sous des contraintes fortes pour les largeurs de bande mises en jeu, en raison notamment des fréquences très élevées utilisées. Ces conditions opérationnelles accentuent les imperfections des dispositifs électroniques réalisant l'échantillonnage et induisent le choix de modèles de signaux et de schémas d'échantillonnage spécifiques. Cette thèse a pour objectif général d'identifier des modèles d'échantillonnage adaptés à ce cadre applicatif. Ceux-ci s'appliquent à des signaux aléatoires passe-bande, qui constituent un modèle classique en télécommunications. Ils doivent prendre en compte des facteurs technologiques, économiques ainsi que des contraintes bord de complexité et éventuellement intégrer des fonctionnalités propres aux télécommunications. La première contribution de cette thèse est de développer des formules d'échantillonnage non uniforme qui intègrent dans le domaine numérique des fonctionnalités délicates à implémenter dans le domaine analogique aux fréquences considérées. La deuxième contribution consiste à caractériser et à compenser les erreurs de synchronisation de dispositifs d'échantillonnage non uniforme particuliers, à savoir les convertisseurs analogique-numérique entrelacés temporellement, via des méthodes supervisées ou aveugles. / The theory of uniform sampling, developed among others by C. Shannon, is the foundation of today digital signal processing. Since then, numerous works have been dedicated to non uniform sampling schemes. On the one hand, these schemes model uniform sampling device imperfections. On the other hand, sampling can be intentionally performed in a non uniform way to benefit from specific properties, in particular simplifications concerning the choice of the mean sampling frequency. Most of these works have focused on theoretical approaches, adopting simplified models for signals and sampling devices. However, in many application domains, such as satellite communications, analog-to-digital conversion is submitted to strong constraints over the involved bandwidth due to the very high frequencies used. These operational conditions enhance the imperfections of the involved electronic devices and require the choice of particular signal models and sampling schemes. This thesis aims at proposing sampling models suitable for this context. These models apply to random band-pass signals, which are the classical models for telecommunication signals. They must take into account technological, economical factors and on-board complexity constraints and allow to integrate particular functionalities useful for telecommunication applications. This thesis first contribution is to develop non uniform sampling formulas that can digitally integrate functionalities that appear to be tricky in the analog domain at the considered frequencies. The thesis second contribution consists in applying non uniform sampling theory to the estimation and compensation of synchronization errors encountered in particular sampling devices, the timeinterleaved analog-to-digital converters. This estimation will be performed through supervised or blind methods.

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

L’utilisation de thérapies ciblées afin d’augmenter la fenêtre thérapeutique des traitements, notamment en oncologie, se développe de plus en plus. Les immunoconjugués font partie de l’arsenal de ces thérapies ciblées. En effet, il s’agit de vectoriser, grâce à un anticorps ciblant un antigène surexprimé sur les cellules cancéreuses, une molécule hautement cytotoxique comme les dérivés d’auristatines. L’espèce résultant est appelée antibody-drug conjugate (ADC). Ce faisant, l’efficacité du composé est augmentée et les potentiels effets secondaires sont limités. Plusieurs technologies permettant l’accroche de l’agent cytotoxique à l’anticorps existent avec différents dégrés d’homogénéité du produit final et différents niveaux de difficultés de mise en œuvre. De nos jours, les avancées technologiques permettent de concevoir des immunoconjugués (ADCs) présentant un chargement en molécule cytotoxique (DAR, drug-to-antibody ratio) contrôlé du point de vue du nombre et de la position (régio-spécifique). / The use of targeted therapies in order to increase the therapeutic window of treatments, especially in oncology, is growing. Immunoconjugates are part of the arsenal of these targeted therapies. Indeed, they aim at delivering, thanks to an antibody directed against overexpressed cancer cell antigens, a highly cytotoxic molecule like auristatins derivatives. The resulting species is called an antibody-drug-conjugate (ADC). By doing so, efficacy of the compound is increased and potential side-effects are limited. Several technologies for grafting the cytotoxic agent to the antibody exist with different levels of homogeneity of the final compound and different levels of difficulty of implementation. Nowadays, technological breakthroughs permit the design of immunoconjugates (ADCs) displaying a controlled drug-to-antibody ratio (DAR) in terms of quantity and position (site-specific).

Com o aumento das aplicações e dispositivos para Internet das Coisas, muitos esforços para reduzir potência dissipada nos transceptores foram investidos. A maioria deles, entretanto, focam individualmente no rádio, nos conversores analógicos para digital e viceversa, e na arquitetura de banda base digital. Como consequência, há pouca margem para melhorias na potência dissipada nestes blocos isolados que compense o enorme esforço. Portanto, este trabalho propõe uma arquitetura adaptativa a nível de sistema focando em reduzir o consumo no conversor analógico para digital e no receptor digital. Ele utiliza um algoritmo robusto para o receptor banda base digital, um conversor analógico para digital topologia Sigma-Delta e um bloco de controle realimentado conforme a relação sinal ruído medida do pacote recebido. O sistema foi projetado para o protocolo IEEE 802.15.4. Para validação do sistema e estimar a potência consumida foi feito um modelo de sistema utilizando a ferramenta Matlab, uma descrição do hardware em linguagem Verilog e uma síntese lógica utilizando o processo da X-FAB XC018. As simulações mostram uma redução na potência consumida pelo sistema de até 13% e ainda atingindo os requisitos do protocolo. Os resultados deste trabalho foram publicados na conferência internacional em tecnologia de instrumentação e medidas de 2014 realizada na cidade de Montevidéu no Uruguai. / With the increase of Internet of Things applications and devices, many efforts to reduce power consumption in transceiver has been invested. Most of them targeted in RF frontend, converters, or in the digital baseband architecture individually. As result, there are few margins nowadays for power improvement in these blocks singly that compensates the huge hard work required. The next optimization step leads to a system level analysis seeking design space and new possibilities expansion. It is in this field that adaptive systems approaches are conquering ground recently. The solutions combines Radio Frequency (RF) and process variation techniques, Low Pass Filters (LPF) and Analog to Digital Converters (ADCs) adjustment for better performance, digital baseband bit width adaptive according to income packet SNR, configurable ADC resolution and topology, and others. In this scenario the current work proposes an adaptive system level architecture targeting ADC and digital receiver power reduction. It uses a robust algorithm for digital baseband receiver, a Sigma-Delta ADC, and suggests a feedback control block based on packet SNR measure. The system was designed for the IEEE 802.15.4 standard and required system modeling using Matlab tool, hardware description in Verilog language, and logic synthesis using X-FAB XC018 process for validation and power consumption estimation. Simulations show up to 15% of system power reduction and still meeting the standard requirements. The work results were published in the International Instrumentation and Measurement Technology Conference of 2014 occurred in Montevideo - Uruguay.

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.

In this study, after-death communication (ADC) is defined as spontaneously occurring encounters with the deceased. Reported occurrences of ADC phenomena range widely among published ADC research studies, so a systematic review of 35 studies was conducted. A rubric was developed to evaluate the methodological quality; final inter-rater reliability among three raters was r = .90. Results were used to rank the studies; the methodologically strongest studies were used to arrive at best estimate answers to four research questions/subquestions: (1) How common are experiences of ADC? How does occurrence vary by gender, age, marital status, ethnicity, religious practice, religious affiliation, financial status, physical health, educational level, and grief status? (2) To what extent do ADCrs report ADC experiences to be beneficial and/or detrimental? What are the leading benefits and/or detriments? (3) What is the incidence of research studies in which the researchers mentioned that the research participants appeared mentally healthy? (4) What is the incidence of sensory modalities—for example, visual, auditory, and kinesthetic—in which ADCs occur? Best estimate results were compiled into a one-page fact sheet that counselors and others can use to educate people who seek empirically-based information about ADC.

This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in order to best follow the input in real time. It uses Flash and Successive Approximation (SAR) conversion techniques in sequence. As part of the design, the concept of "total real-time optimization" is explored, where any delay at all is treated as an error (Error = Delay * Signal Slew Rate). This error metric is proposed for use in digital control systems. The ADC uses a 4-bit Flash converter in tandem with SAR logic that has variable precision (0 to 11 bits). This allows the Tandem ADC to switch from a fast, imprecise converter to a slow, precise converter. The level of precision is determined by the input’s peak rate of change, optimized for minimum real-time error; a secondary goal is to react quickly to input transient spikes. The implementation of the Tandem ADC is described, along with various issues which arise when designing such a converter and how they may be dealt with. These include Flash ADC inaccuracies, rounding issues, and system timing and synchronization. Most of the design is described down to the level of logic gates and related building blocks (e.g. latches and flip-flops), and various logic optimizations are used in the design to reduce calculation delays. The design also avoids active analog circuitry whenever possible – it can be almost entirely implemented with CMOS logic and passive analog components.

This Graduate Thesis is about communication module for optical wireless network. This device read data from RS232 port and two analog inputs and sends it through internet to a remote Computer. Furthermore allows voice communication between local user on module and user on remote computer. Device allows communication with standard headphones and microphone, or with Bluetooth handsfree. Basic part is microprocessor MCF5223 and Bluetooth Ezurio BISM II module. Control program has been written in C language. Printed circuit is created by EAGLE program. This device is managed via web interface and settings have been stored into EEPROM memory. Work contains description of separately parts and blocks, source code of program, description of source code and printed circuit designs.

Design step for Sigma-Delta ADC is introduced. Suitable solution for performance improvement of the original Sigma-Delta ADC, which meets new requirements on resolution of 16 bits and signal bandwidth 20-50 kHz is presented. Advantage of using multi-bit quantization and DEM DWA method reducing the linearity requirements of the internal feedback DAC is shown.

This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.