Les travaux de recherche de cette thèse de doctorat s’inscrivent dans le cadre de la conception d’unconvertisseur analogique-numérique (ADC, Analog-to-Digital Converter) large bande et à haute résolution afinde numériser plusieurs standards de communications sans fil. Il répond ainsi au concept de la radio logiciellerestreinte (SDR, Software Defined Radio). L’objectif visé est la reconfigurabilité par logiciel et l’intégrabilité envue d’un système radio multistandard. Les ADCs à sur-échantillonnage de type sigma-delta () s’avèrent debons candidats dans ce contexte de réception SDR multistandard en raison de leur précision accrue. Bien queleur bande passante soit réduite, il est possible de les utiliser dans une architecture en parallèle permettantd’élargir la bande passante. Nous nous proposons alors dans cette thèse de dimensionner et d’implanter unADC parallèle à décomposition fréquentielle (FBD) basé sur des modulateurs  à temps-discret pour unrécepteur SDR supportant les standards E-GSM, UMTS et IEEE802.11a. La nouveauté dans l’architectureproposée est qu’il est programmable, la numérisation d’un signal issu d’un standard donné se réalise enactivant seulement les branches concernées de l’architecture parallèle avec des sous-bandes defonctionnement et une fréquence d’échantillonnage spécifiée. De plus, le partage fréquentiel des sous-bandesest non uniforme. Après validation du dimensionnement théorique par simulation, l’étage en bande de base aété dimensionné. Cette étude conduit à la définition d’un filtre anti-repliement passif unique d’ordre 6 et detype Butterworth, permettant l’élimination du circuit de contrôle de gain automatique (AGC). L’architectureFBD requière un traitement numérique permettant de combiner les signaux à la sortie des branches enparallèle pour reconstruire le signal de sortie finale. Un dimensionnement optimisé de cet étage numérique àbase de démodulation a été proposé. La synthèse de l’étage en bande de base a montré des problèmes destabilité des modulateurs . Pour y remédier, une solution basée sur la modification de la fonction detransfert du signal (STF) afin de filtrer les signaux hors bande d’intérêt par branche a été élaborée. Unediscontinuité de phase a été également constatée dans le signal de sortie reconstruit. Une solution deraccordement de phase a été proposée. L’étude analytique et la conception niveau système ont étécomplétées par une implantation de la reconstruction numérique de l’ADC parallèle. Deux flots de conceptionont été considérés, un associé au FPGA et l’autre indépendant de la cible choisie (VHDL standard).L’architecture proposée a été validée sur un FPGA Xilinx de type VIRTEX6. Une dynamique de 74 dB a étémesurée pour le cas d’étude UMTS, ce qui est compatible avec celle requise du standard UMTS. / The work presented in this Ph.D. dissertation deals with the design of a wideband and accurate Analog-to-Digital Converter (ADC) able to digitize signals of different wireless communications standards. Thereby, itresponds to the Software Defined Radio concept (SDR). The purpose is reconfigurability by software andintegrability of the multistandard radio terminal. Oversampling  (Sigma Delta) ADCs have been interestingcandidates in this context of multistandard SDR reception thanks to their high accuracy. Although they presentlimited operating bandwidth, it is possible to use them in a parallel architecture thus the bandwidth isextended. Therefore, we propose in this work the design and implementation of a parallel frequency banddecomposition ADC based on Discrete-time  modulators in an SDR receiver handling E-GSM, UMTS andIEEE802.11a standard signals. The novelty of this proposed architecture is its programmability. Where,according to the selected standard digitization is made by activating only required branches are activated withspecified sub-bandwidths and sampling frequency. In addition the frequency division plan is non-uniform.After validation of the theoretical design by simulation, the overall baseband stage has been designed. Resultsof this study have led to a single passive 6th order Butterworth anti-aliasing filter (AAF) permitting theelimination of the automatic gain control circuit (AGC) which is an analog component. FBD architecturerequires digital processing able to recombine parallel branches outputs signals in order to reconstruct the finaloutput signal. An optimized design of this digital reconstruction signal stage has been proposed. Synthesis ofthe baseband stage has revealed  modulators stability problems. To deal with this problem, a solution basedon non-unitary STF has been elaborated. Indeed, phase mismatches have been shown in the recombinedoutput signal and they have been corrected in the digital stage. Analytic study and system level design havebeen completed by an implementation of the parallel ADC digital reconstruction stage. Two design flows havebeen considered, one associated to the FPGA and another independent of the chosen target (standard VHDL).Proposed architecture has been validated using a VIRTEX6 FPGA Xilinx target. A dynamic range over 74 dB hasbeen measured for UMTS use case, which responds to the dynamic range required by this standard.

L'objectif de cette thèse est de développer et d'évaluer des paramètres quantitatifs de l'IRM de la prostate en discriminant les cancers de score de Gleason (GS) ≥7. Nous supposons que les paramètres quantitatifs de l'IRM pourraient aider à standardiser le diagnostic, et à diminuer la variation inter-lecteur et/ou inter-institution du diagnostic du cancer de la prostate. Cette thèse est divisée en trois chapitres. Le premier chapitre, intitulé « IRM T2 quantitatif de la prostate », est une étude rétrospective sur une base de données des patients avant prostatectomie radicale. Le deuxième chapitre, intitulé « IRM multiparamétrique quantitative de la prostate », est aussi une étude rétrospective avant prostatectomie radicale. Le troisième chapitre, intitulé « Élastographie IRM de la prostate par voie trans-périnéale» est une étude expérimentale. Notre première étude montre que le T2 est robuste sur les machines de constructeurs différents. Le T2 est un prédicteur significatif, mais de faible performance, d'agressivité du cancer de la prostate à 3T. Notre deuxième étude montre que la combinaison du 10ème centile de l'ADC avec le Time-topeak (TTP) améliore la performance du diagnostic, et ce modèle est lui aussi robuste entre des machines de constructeurs différents. Notre troisième étude montre les résultats préliminaires sur l'élasticité de la prostate. Ces résultats montrent que l'élastographie IRM de la prostate en haute fréquence d'excitation (>100 Hz) par voie trans-périnéale est faisable. L'élastographie pourrait à l'avenir être intégrée à l'IRM multiparamétrique quantitative pour améliorer la performance de diagnostic / The purpose of this thesis is to develop and evaluate the quantitative methods of multiparametric MRI of prostate in discriminating Gleason score (GS) ≥7 cancers. We suppose that the quantitative parameter of MRI could help standardizer the diagnostic, reduce the inter-lecture and/ or inter-institution variation in diagnostic of prostate cancer. This thesis is divided into three chapters. The firs chapter, entilted « Quantitative T2 MRI of prostate » is a retrospective study on a database of prostate cancer patients before radical prostatectomy. The second chapter, entilted « Multi-parametric Quantitative MRI of prostate » is also a retrospective study before radical prostatectomy. The third chapter, entitled « MR elastography of prostate by transperineal approach », is an experimental study. Our first study shows that T2 value is robust between machines of different constructors. T2 value is significant predictor, but of weak performance, of aggressively cancer of prostate at 3T. Our second study shows that the combination of ADC_10th percentile with Time-to-peak (TTP) improved the diagnosis performance, and this model is also robust between two machines of different constructors. Our third study shows the initial results on elasticity of the prostate. These results show that MRI elastography of prostate at high excitation frequency (>100 Hz) by trans-perineale approach was feasible. The elastography may, in the future, be integrated in quantitative multi-parametric MRI to improve the diagnosis performance

De nombreux dispositifs embarqués récents comme les téléphones portables, les GPS ou encore les consoles de jeu, possèdent un ou des haut-parleurs, chacun étant piloté par un amplificateur audio sur circuit intégré. De tels amplificateurs audio doivent répondre le mieux possible à quatre contraintes : une qualité audio satisfaisante, une immunité aux perturbations induites par le système, une faible consommation et une surface de silicium minimale. Ce travail de thèse sous contrat CIFRE a pour origine la création de l’entreprise Primachip en mai 2009 par Christian Dufaza et Hassan Ihs. Cette startup a été bâtie sur une architecture innovante d’amplificateur audio de classe D intégré. Son originalité repose sur le principe de rétroaction partielle qui s’applique à une boucle contenant un modulateur numérique Delta Sigma (ΔΣ) qui pilote l’étage de puissance et un convertisseur analogique-numérique (ADC) effectuant la rétroaction. Cela permet d’obtenir la stabilité de cette boucle tout en offrant une excellente réjection des bruits de l’étage de puissance. Un prototype sur silicium de l’architecture d’amplificateur de classe D numérique a été conçu et fabriqué. Un nouvel ADC ΔΣ temps continu a été développé pour ce prototype, afin d’obtenir des performances supérieures ou égales à l’état de l’art. Les résultats obtenus sur le circuit se sont révélés encourageants, bien que toutes les spécifications n’aient pas été atteintes. L’analyse des erreurs de ce premier circuit doit permettre la réalisation d’un amplificateur intégré exploitant au mieux cette architecture de classe D numérique. / Most current embedded devices, such as smartphones, GPS or portable consoles, feature one speaker or more, those speakers being driven by an integrated audio amplifier. This type of amplifier must meet four specifications: an adequate audio quality, to be immune to system disturbances, low power consumption and the smallest silicon area. This work takes its origin from the creation of Primachip in May 2009 by Christian Dufaza and Hassan Ihs. The aim of this startup was to develop and sell an innovative audio class-D amplifier for mobile market: the digital class-D concept. A partnership with the IM2NP laboratory was decided to propose a PhD topic under CIFRE contract (PhD in an industrial environment), in order to study and improve the amplifier architecture. Its originality is in the partial feedback concept which applies to a loop made of a digital ΔΣ modulator driving the power stage, with an analogue-to-digital converter (ADC) in the feedback path. It makes it possible to achieve stability while offering an outstanding power supply rejection. An integrated prototype of the class-D amplifier was designed, fabricated and evaluated. A new continuous-time ΔΣ ADC has been added to enable the digital class-D loop to achieve performances superior or equal to state of the art. The circuit measurement results were encouraging, although not ideal. The analysis of the prototype errors was performed. The conclusions should allow the design of an integrated audio amplifier making the best of the digital class-D architecture.

Purpose of this dissertation is to explore control techniques of PMSM motors and the design of a complex solution of sensorless control across a wide range of speed and torque. The proposed solution supports industrial implementation of different types of end equipment which use a PMSM motor. The work covers a thorough analysis of position and speed estimation. The Control structure is based on field oriented control technique, processes estimated quantities, and optimizes motor conditions to achieve maximum efficiency, start-up torque, and speed. The work discusses how the solution complies with the latest IEC standards. Compliance with these standards requires adapting the sensorless control technique and field oriented control structure. The elimination of a rotor position sensor and a temperature sensor measuring winding temperature requires development of techniques in software for blocked rotor detection and overload detection. The proposed solutions, which have been granted US patents, are explained in this work and utilize the unique features of an NXP microcontroller optimized for motor control applications. The achieved results are demonstrated on real industrial applications.

Táto diplomová práca sa zaoberá návrhom zariadenia schopného vysoko presného merania vibrácií za použitia piezoelektrického akcelerometra. Zariadenie je určené na vyhodnocovanie zdravotného stavu strojov, najmä elektrických strojov ako elektromotor, veterná turbína a iné. Za účelom dosiahnutia vysoko presného a vysoko lineárneho merania v spektre extrémne nízkych frekvencií siahajúcich až ku jednosmerným napätím, cez sub-hertzové pásma po desiatky hertzov, ale aj vo vyšších frekvenciách, bola vyžadovaná možnosť použitia prístupu s jednosmernou väzbou zvaného "posúvanie napäťovej úrovne" a následné vyhodnotenie a porovnanie prístupu so striedavou väzbou, ktorý sa bežne používa pre pripojenie piezoelektrického akcelerometra.

Inledning: Uteruscancer är den sjätte vanligaste cancerformen hos kvinnor i världen. Ny forskning pekar på att diffusionsviktad magnetresonanstomografi (MRT) kan vara en tillförlitlig undersökningsmetod för att detektera patologiska förändringar i uterus. Syfte: Att skapa en översikt av användbarheten av diffusionsviktade sekvenser vid MRT för att påvisa uteruscancer. Metod: Allmän litteraturöversikt, tio kvantitativa studier inkluderades. Resultat: Diffusionsviktade sekvenser vid MRT har högre sensitivitet, specificitet samt diagnostisk noggrannhet för att påvisa patologiska förändringar i uterus än sekvenser utan diffusionsviktning. Apparent diffusion coefficient (ADC) och b-värden är viktiga markörer för att skilja malign från benign vävnad, indikera patologisk parametrieinvasion samt förutse överlevnad hos patienter med cervixcancer. Slutsats: Diffusionsviktade sekvenser är bättre än sekvenser utan diffusionsviktning och kontrastmedelsförstärkta sekvenser på att hitta samt stadieindela tidiga förändringar i uterus. Undersökningen görs non-invasiv och säker för patienter med känslighet eller allergi mot kontrastmedel, samt frigör tid för röntgensjuksköterskan till omvårdnad av patienten. / Background: Uterus cancer is the sixth most common form of cancer in women in the world. New research suggests that diffusion-weighted magnetic resonance imaging (MRI) can be a reliable method of investigation for detecting pathological changes in the uterus. Purpose: To provide an overview of the available scientific support for the use of diffusion-weighted sequences in MRI to detect uterine cancer. Method: Literature review that included ten quantitative studies. Results: Diffusion-weighted sequences in MRI have higher sensitivity, specificity and diagnostic accuracy to detect pathological changes in the uterus compared to non- diffusion-weighted sequences. Apparent diffusion coefficient (ADC) and b-values are important markers to distinguish malignant from benign tissue, indicate pathological parametric invasion, and predict survival in patients with cervical cancer. Conclusion: Diffusion-weighted sequences are better than sequences without diffusion-weighting and contrast-mediated sequences for identifying and staging early changes in the uterus. The examination is made non-invasive and safe for patients with sensitivity or allergies toward contrast media, as well as freeing time for the radiographer to care for the patient.

The rapid development in the semiconductors industry has enabled the placement of multiple chips on a single die. This has helped boost the functionality of modernday application specific integrated circuits (ASICs). Thus, digital circuits are being increasingly placed along-side analog and RF circuits in what are known as mixed signal circuits. As a result, the noise couplings through the substrate now have an increased role in mixed-signal ASIC design. Therefore, there is a need to study the effects of substrate noise and include them in the traditional design methodology. ∆Σ analog-to-digital converters (ADCs) are a perfect example of digital integration in traditionally analog circuits. ADCs, used to interface digital circuits to an analog world, are indispensable in mixed-signal systems and therefore set an interesting case study. A ∆Σ ADC is used in this thesis to study the effects of substrate noise. A background study is presented in the thesis to better understand ∆Σ modulators and substrate couplings. An intensive theoretical background on generation, propagation and reception of substrate noise is presented in light of existing researches. System and behavioural level models are proposed to include the effects of substrate noise in the design stages. A maximum decay of 10dB is seen due to injection of substrate noise system level simulations while a decay of 12dB is seen in behavioural simulations. A solution is proposed using controlled clock tree delays to overcome the effects of substrate noise. The solution is verified on both the system and behavioural levels. The noise models used to drive the studies can further be used in mixed-signal systems to design custom solutions. / Den snabba utvecklingen inom halvledarindustrin har möjliggjort placering av flera marker på en enda dö. Detta har hjälpt till att öka funktionaliteten hos moderna applikationsspecifika integrerade kretsar. Sålunda placeras digitala kretsar i allt högre grad parallella och RF-kretsar i de så kallade blandade signalkretsarna. Som ett resultat har bullerkopplingarna genom substratet nu en ökad roll i ASICdesign med blandad signal. Därför finns det behov av att studera effekterna av substratbuller och inkludera dem i den traditionella designmetoden. ∆Σ analog-till-digital omvandlare är ett perfekt exempel på digital integration i traditionellt analoga kretsar. ADC, som används för att gränssnitta digitala kretsar till en analog värld, är oumbärliga i blandningssignalsystem och är därför en intressant fallstudie. A ∆Σ arkitektur används i denna avhandling för att studera effekterna av substratstörning. En bakgrundsstudie presenteras i avhandlingen för att bättre förstå ∆Σ modulatorer och substratkopplingar. En intensiv teoretisk bakgrund på generering, förökning och mottagande av substratbuller presenteras i ljuset av befintliga undersökningar. Systemoch beteendemodellmodeller föreslås inkludera effekterna av substratbuller i konstruktionsstadiet. Ett maximalt förfall på 10dB ses på grund av injektion av substratbuller på systemnivå medan ett förfall av 12dB ses i beteende simuleringar.En lösning föreslås med hjälp av kontrollerade klockträdfördröjningar för att övervinna effekterna av substratbuller. Lösningen är verifierad på både system och beteendenivåer. De brusmodeller som används för att driva studierna kan vidare användas i blandningssignalsystem för att designa anpassade lösningar.

This thesis report is about designing a prototype and establishing audio communication between a computer and Digital Signal Processor (DSP) using two preamp circuits using both auxiliary and USB connection. The paper gives the reader an overview on how audio is transmitted from a computer, through the system and to the desired output. The reader should also get a better understanding of how an AD-converter samples the incoming signal to the Discrete plane and how an AUX or phone connector works. This information can be used for designing preamp circuits to communicate between a computer and the DSP. The DSP circuit uses an STM32 processor to control the incoming and outgoing signals with the use of ADC and DAC conversion. The DSP also uses microphones to capture surrounding sound. An addition is to make a prototype on how to use these microphones to  send the signal upstream to the computer. The microphone is then benchmarked with the use of Matlab, calculating Total Harmonic Distortion. Management and optimization of code structure and resources is done in the source files of the project. Using imperative C programing, large functions are broken down into smaller functions to ease readability and control flow. The result is a prototype circuit that can communicate audio signals with both audio jack and USB between computers input and output to the DSP. Using CubeMX in conjunction with CubeIDE to add additional ADC channels to be able to incorporate an automatic source control when the audio jack or USB is connected. / Denna avhandling handlar om att designa en prototyp och etablera ljudkommunikation mellan en dator och en digital signalprocessor (DSP) med hjälp av två förstärkarkretsar genom både aux- och USB-anslutning. Rapporten ger läsaren en översikt över hur ljud skickas från en dator, genom systemet och till önskad utgång. Läsaren bör också få en bättre förståelse för hur en AD-omvandlare fungerar för att sampla den inkommande signalen till tidsdiskreta planet och hur en AUX- eller telekabel fungerar. Målet är att använda denna information för att skapa förstärkare som kan kommunicera mellan en dator och DSP:en. DSP-kretsen använder en STM32-processor för att hantera de inkommande och utgående signalerna med användning av ADC- och DAC-omvandling. DSP:en använder också mikrofoner för att fånga omgivande ljud. Ett tillägg är att skapa en prototyp för hur man kan använda en av mikrofonerna för att skicka signalen till datorn. Mikrofonen jämförs sedan med hjälp av Matlab genom att beräkna total harmonisk distorsion. Hantering och optimering av kodstruktur och resurser görs i projektets källkodsfiler. Genom att använda imperativ C-programmering bryts stora funktioner ned i mindre funktioner för att underlätta läsbarheten och styrningen av flödet. Resultatet är en prototypkrets som kan kommunicera ljudsignaler med både ljuduttag och USB mellan datorns in- och utgång och DSP:en. Genom att använda CubeMX tillsammans med CubeIDE läggs ytterligare ADC-kanaler för att möjliggöra automatisk källkontroll när ljuduttaget eller USB-anslutningen är ansluten.

High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW. The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW. A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done. / <p>Report code: LiU-Tek-Lic-2005:68.</p>

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.