Les Thrombopénies Induites par l’Héparine (TIH) sont une complication sévère des traitements par l’héparine dues à des IgG qui ciblent le facteur plaquettaire 4 modifié par l’héparine (FP4/H) et induisent une activation cellulaire via FcγRIIA, conduisant à des complications thrombotiques. Nous avons caractérisé 5B9, IgG1 monoclonale chimérique anti-FP4/H mimant parfaitement les anticorps de TIH et qui est donc un excellent outil pour étudier la physiopathologie des TIH. La pathogénicité des anticorps (Ac) de TIH implique leur fixation aux FcγR. Nous avons montré que le clivage de la région charnière des IgG de TIH par IdeS inhibe ces interactions IgG-FcγR et supprime la pathogénicité des Ac. Nous avons aussi construit un Antibody-Drug Conjugate (ADC) antithrombotique, en bioconjuguant le tirofiban (inhibiteur de l’agrégation plaquettaire) et 5B9 déglycosylé grâce à un linker clivable par la thrombine, protéase générée en excès lors d’une TIH. / Heparin Induced Thrombocytopenia (HIT) is a rare but severe complication of heparin treatments. HIT is due to IgG antibodies specific to platelet factor 4 modified by heparin (PF4/H), which activate blood cells, (especially platelets) after binding to FcγRIIA, this process explaining frequent thrombotic complications. We characterized 5B9, a chimeric IgG1 targeting PF4/H and which fully mimics human HIT antibodies. Therefore, 5B9 is a perfect tool for studying the physiopathology of HIT. IgG antibodies to PF4/H are pathogenic by interacting with FcγR. In this regard, we showed that cleavage by IdeS, a bacterial protease, of the hinge of anti-PF4/H IgG, fully suppressed their pathogenicity. Furthermore, we designed an antithrombotic Antibody-Drug Conjugate that combined tirofiban, a GPIIbIIIa inhibitor with deglycosylated 5B9 using a thrombin cleavable linker.

<p>LC-MS of protein drugs requires new ideas in bonded phase design rather than adapting bonded phases from the realm of small-molecule drugs. The polymer-shell bonded phase is designed to interact with larger molecules and to shield proteins from the silica substrate. The particles consist of a core of solid silica and a shell of dense polymer brush. The polymer layer is thick enough to protect the protein from interactions with silanols to reduce peak tailing. The polymer contains multiple functional groups that introduce more selectivity. This design gives unprecedented LC resolution and MS sensitivity. Our group has developed polymer shell bonded phases for hydrophobic interaction chromatography (HIC-MS) of antibody-drug conjugates (ADCs), hydrophilic interaction liquid chromatography (HILIC-MS) of glycoproteins, and reversed-phase liquid chromatography (RPLC-MS) of monoclonal antibodies. Since HIC is not in-line compatible with MS due to the high salt levels, it is laborious to identify the constituents of HIC peaks. An MS-compatible alternative to HIC is reported here: native reversed phase liquid chromatography (nRPLC). This employs a mobile phase 50 mM ammonium acetate for high sensitivity in MS, and elution with a gradient of water/isopropanol. The nRPLC-MS data show that all ADC species, ranging from drug-to-antibody ratios of 1 to 8, remained intact and native on the column. As we adapt this concept to intact proteins, we find that lysozyme and α-chymotrypsinogen A are both eluted in their native conformations. We also use the polymer-shell concept to resolve IgG1 free thiol variants by RPLC-MS with 0.5% formic acid. Since there are always other variants besides the intended ones, the need for high MS sensitivity is desired to distinguish subtle mass change between disulfide bond and free thiols. Overall, MS sensitivity increases 10X relative while all of the thiol variants are well resolved by the polymethylmethacrylate bonded phase.</p>

Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues are extremely helpful for curing many neural injuries and cognitive diseases. One method to discover this field is by designing a chip embedded in brains with probes to actual neurons. It is obvious that batteries are not practical for these applications and thereby RF radiation is used as power sources, revealing that chips should operate under a very low power supply. Since neural signals are analog waveforms, analog-to-digital converter (A/D converter, ADC) is the key component in a neural recorder chip. This thesis proposes the complete design of a low power 8-bit successive approximation register (SAR) A/D converter for use in a wireless neural recorder chip, realizing the function of digitizing a sampled neural signal with a frequency distribution of 10Hz to 10kHz. A modified energy-saving capacitor array in the SAR structure is provided to help save power dissipation. Therefore, the ADC shall operate within a power budget of 20­μW maximum from a 1­V power source, at a clock frequency of 500kHz corresponding to a conversion rate of 55.5-kS/s. All the circuits are designed and implemented based on the IBM/Global Foundries 8HP 130nm BiCMOS technology. Simulations of schematic and layout versions are done respectively to verify the functionality, linearity and power consumption of the ADC. Key words: Successive approximation register analog-to-digital converter (SAR-ADC), low power design, energy-saving capacitor array, neural recorder applications

In this thesis will be described research towards the development of bioorthogonal bond-cleavage reactions, and their applications in targeted drug delivery (Figure 1). The first project relates to the development of a palladium mediated bond-cleavage or "decaging" reaction which can cause a propargyl carbamate to decompose and release an amine. This was further developed by the incorporation of a protein modification handle which allowed an amine-bearing drug to be covalently ligated to a protein by a palladium-cleavable linker. This chemistry was demonstrated by the conjugation of the anticancer drug doxorubicin to a tumour targeted anti-HER2 nanobody. The drug could then be delivered to cancer cells upon addition of a palladium complex. The second project relates to the development of a platinum mediated bond-cleavage reaction. This was developed with the aim of using platinum-containing anticancer drugs - such as cisplatin - as a catalyst to cause drug release reactions in tumours. In this reaction an alkyne-containing amide can decompose to release an amine upon addition of platinum complexes, and was applied to the release of prodrugs of the cytotoxins monomethylauristatin E and 5-fluorouracil in cancer cells. A cisplatin-cleavable antibody-drug conjugate was designed and synthesised, and progress towards its biological evaluation will be discussed.

abstract: This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW power. Another example achieves 78.2dB SNR in 31.25µs measurement time and consumes 63µW power. The second ADC architecture is a multi-mode, dynamically zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)- independent, dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW power consumption from a 1.2 V supply. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Les convertisseurs analogiques-numériques fondés sur le principe de la modulation §¢ sont capables de fonctionner à des résolutions très élevés. L'utilisation en interne d'un CAN et d'un CNA multibit permet de réduire le taux de suréchantillonnage, les contraintes imposées par les circuits actifs, amé- liore la stabilité de la boucle du modulateur, mais rend celui-ci très sensible aux imperfections des composants du convertisseur numérique analogique (CNA) interne situé dans le chemin de retour. Les erreurs statiques dues aux non idéalités des circuits constitutifs de ce CNA peuvent être corrigées au moyen de techniques d'appariement dynamique des composants (DEM). Ce travail de thèse est consacré entre autre à l'étude théorique de ces techniques de correction des défauts des cellules des CNA multibits. Après avoir rappelé le principe de la conversion §¢ d'une part, et les différentes sources d'erreurs dominantes dans le cas multibit d'autre part, les techniques d'appariement existantes sont analysées et comparées. Nous soulignons les avantages, les inconvénients, et les domaines d'applications préférentiels de chacune. Le coeur du travail consiste en la proposition de quatre nouvelles techniques d'appariement dynamique. Les deux premières dérivent de la méthode de la moyenne des données (DWA), l'une pour le cas passe-bas du premier ordre, l'autre dans le cas passe-bande du second ordre. Les deux dernières propositions (appelées MDEM et STDEM) dérivent des deux algorithmes de tri (SDEM) et d'arborescence (TDEM) : elles conviennent à une mise en forme des erreurs d'ordre élevé et sont destinées aux applications passe-bas et passe-bande de haute performance. Ces quatre méthodes proposées ont été mises en équation et leurs performances confirmées par diverses simulations. Une implantation des algorithmes MDEM et STDEM a été faite au niveau cellule standard jusqu'à l'étape finale de routage en technologie CMOS 0.35 ¹m. L'ensemble des résultats des simulations au niveau système et au niveau transistor conforme l'avantage des techniques développées dans ce travail en termes de surface occupée et aussi de fréquence maximale d'application, si on les compare avec les algorithmes conventionnels de SDEM. Dans une dernière partie, les erreurs dynamiques du CNA, en particulier l'effet de la gigue d'horloge, le glitch, la dissymétrie des temps de transition, l'injection de charge (CFT) et la métastabilité du quantificateur sont également analysés. A l'issue de ces réflexions, une nouvelle cellule de CNA incluant un bloc limitant la plage dynamique de la commande d'entrée (SRD) est proposée. Elle possède une structure de remise à zéro partielle (semi-RZ) qui permet de bénéficier à la fois de l'avantage de la cellule RZ et non RZ. De plus, l'effet du retard du bloc de DEM est compensé par une modification dans l'architecture convenant aux applications passe-bande haute fréquence.

Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures. In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs. / Graduation date: 2011

A major challenge faced by project managers is balancing the variables of scope, cost, and schedule. Changes in scope usually result in cost/schedule overruns. Variance in either or both of them creates disorder (typically increases) in the estimated or projected time and cost. Therefore, controlling cost and schedule are two of the most critical aspects of a construction project. This research uses two already existing management theories, specifically Management by Means (MBM) and Management by Results (MBR), and analyzes a case where these two theories are combined with the goal of improving construction practices. This research compares an eight month schedule in a construction project and relates Percentage of Planned activities Completed (PPC) with projected and actual draw (cash) calls. The research analyzes the question of how lean construction PPC captures variance in cost. The research method is based on a literature review, data collection, case study and data interpretation to answer the hypothesis that improvement in PPC over a particular month has a positive correlation with difference between cash calls. Because this research is limited to a time frame of 8 months in a single project, it is not statistically significant. However, this research serves to create a model template or pilot study for a larger study.

This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.

This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE) (AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved 4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.