In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Jan. 7, 2013 - Jan. 7, 2014

This project considers the diffusion of water molecules through a cellular medium in which the cells are modeled by square compartments placed symmetrically in a square domain. We assume the diffusion process is governed by the 2D diffusion equations and the solution is provided by implementing the Crank-Nicolson scheme. These results are verified and illustrated to agree well with the finite element method using the Comsol Multiphysics package. The model is used to compute the values of the apparent diffusion coefficient, (ADC) which is a measure that is derived from diffusion weighted MRI data and can be used to identify, e.g., regions of ischemia in the brain. With our model, it is possible to examine how the value of the apparent diffusion coefficient is affected whenever the extracellular space is varied. We observe that the average distance that the water molecules travel in a definite time is highly dependent on the geometrical properties of the cellular media. / UOIT

The goal of this bachelor thesis work was to establish a cable connection between an analogue interface board, containing a 16 bit analogue to digital converter, and a DE2 board in order to allow for digital data transmission between the two boards. The DE2 board includes an FPGA which was configured to contain a Nios II softcore microprocessor for handling the tasks of reading and saving the 16 bit digital words transmitted over the cable as well as controlling the analogue to digital converter on the interface board. During the project work various tasks had to be fulfilled which included soldering the cable for parallel transmission of the 16 bit digital data words and the control signals between the boards as well as adjusting the analogue interface board with the correct voltage supplies and jumper settings. Furthermore the hardware circuit insidethe FPGA had to be configured and the program running on the Nios II processor had to be written in C language.

The filter complexity in the multi-stage decimation system of a Δ-Σ ADC increases progressively as one moves to higher stages of decimation due to the fact that the input word length of the higher stages also increases progressively. The main motivation for this thesis comes from the idea of investigating a way, to reduce the input word length in the later filter stages of the decimation system which could reduce the filter complexity. To achieve this, we use a noise-shaping loop between the first and later stages so that the input word length for the later stages remains smaller than in the case where we do not use the noise-shaping loop. However, the performance (SNR/ Noise-level) level should remain the same in both cases. This thesis aims at analyzing the implications of using a noise-shaping loop in between the decimation stages of a Δ-Σ ADC and also finding the appropriate decimation filter types that could be used in such a decimation system. This thesis also tries to compare the complexity introduced by using the noise-shaping loop with the reduction achieved in the later decimation stages in terms of the input word length. Filter required in the system will also be optimized using minimax optimization technique.

During test flights SAAB uses the data acquisition system COMET 16. The part of the system that receives the signals from the sensors and converts them is called KSM 15. The purpose of this thesis is to develop a data acquisition module on stacked PC/104 modules with a lower production cost. Our work has been divided into one part about analog signal conditioning and a second part with digital filtering and memory management of the sampled data. The analog part, designed of regular components like instrument amplifiers, voltage references, operational amplifiers and multiplexers, adjusts the sensors signal levels for the ADC’s that converts the signals. In the digital part the sampling frequency is decimated by digital FIR filters in several stages down to 16 Hz. All the resulting data is temporarily stored in a SDRAM memory before being recovered by the HL-11 board that handles the communication with the other parts of the COMET system. We have made a design proposal that needs some additional work and testing before a prototype can be made. It’s primarily the C code in the digital part that needs further development. Our result and conclusions should be a great help in the future when developing a small,cheap data acquisition system.

Den här högskoleavhandlingen beskriver framtagningen av en modell för en kombinerad styr- och mätutrustning. Syftet med utrustningen är att använda denna för att underlätta vidare utveckling av organisk elektronik vilket är ett av Acreo AB:s forskningsområden. Istället för att till varje ny komponent eller system utveckla ett nytt testsystem kan denna modell användas på ett generellt sätt, vilket sparar värdefull utvecklingstid. I avhandlingen presenteras först de krav som utrustningen ska uppfylla följt av några förslag på lösningar. Därefter väljs ett av förslagen och en grundläggande implementering genomförs med hänsyn mot kraven. Slutligen innehåller rapporten förslag på hur vidare arbete med modellen kan ske. / This bachelor thesis describes the developing of a model for combined steering and measuring equipment. The purpose is to ease further developing of organic electronics, which is one of Acreo AB’s research areas. A test system is needed for every new component or system developed. Instead of constructing a new test environment for every case this equipment will be a general solution that will save valuable developing time. This thesis will first present the requirements followed by some proposal solutions. Thereafter one proposal will be chosen and an essential implementation will be done with consideration of the requirements. Finally the thesis contains suggestions on how to further develop the model.

In this report a transistor-level design of a GHz Sigma-Delta analog-to-digital converter for an RF front end is proposed. The design is current driven, where the integration is done directly over two capacitances and it contains no operational amplifiers. The clock frequency used for verification was 2.5 GHz and the output band-width was 10 MHz. The system is flexible in that the number of internal bits can be scaled easily and in this report a three-bit system yielding an SNR of 76.5 dB as well as a four-bit system yielding an SNR of 82.5 dB are analyzed.

<p>Advancements of the semiconductor technology opened a new era in</p> <p>wireless communications which led manufacturers to produce faster,</p> <p>more functional devices in much smaller sizes. However, testing</p> <p>these devices of today's technology became much harder and expensive</p> <p>due to the complexity of the devices and the high operating speeds.</p> <p>Moreover, testing these devices becomes more important since decreasing</p> <p>feature sizes increase the probability of parametric and catastrophic</p> <p>faults because of the severe effects of process variations. Manufacturers</p> <p>have to increase their test budgets to address quality and reliability</p> <p>concerns. In the radio frequency (RF) domain, overall test cost are higher</p> <p>due to equipment costs, test development and test time costs. Advanced</p> <p>circuit integration, which integrates various analog and digital circuit</p> <p>blocks into single device, increases test costs further because of the</p> <p>additional tests requiring new test setups with extra test equipments.</p> <p>Today's RF transceiver circuits contain many analog and digital circuit</p> <p>blocks, such as synthesizers, data converters and the analog RF front-end</p> <p>leading to a mixed signal device. Verification of the specifications and</p> <p>functionality of each circuit block and the overall transceiver require</p> <p>RF instrumentation and lengthy test routines. In this dissertation, we</p> <p>propose efficient component and system level test methods for RF</p> <p>transceivers which are low cost alternatives to traditional tests.</p> <p>In the first component level test, we focus on in-band phase noise of the</p> <p>phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at</p> <p>measuring the timing jitter that may require precise reference clocks and/or</p> <p>additional computation of measured specs. We propose a built in test (BiT)</p> <p>circuit to perform a go/no-go test for in-band PLL phase noise. The proposed</p> <p>circuit measures the band-limited noise power at the input of the voltage</p> <p>controlled oscillator (VCO). This noise power is translated as the high</p> <p>frequency in-band phase noise at the output of the PLL. Our circuit contains</p> <p>a self calibration sequence based on a simple sinusoidal input signal to make</p> <p>it robust with respect to process variations.</p> <p>The second component level test is a built in self test (BiST) scheme</p> <p>proposed for analog to digital converters (ADC) based on a linear ramp</p> <p>generator and efficient output analysis. The proposed analysis method is</p> <p>an alternative to histogram based analysis techniques to provide test time</p> <p>improvements, especially when the resources are scarce. In addition to the</p> <p>measurement of differential nonlinearity (DNL) and integral nonlinearity</p> <p>(INL), non-monotonic behavior of the ADC can also be detected with the</p> <p>proposed technique. The proposed ramp generator has a high linearity</p> <p>capable of testing 13-bit ADCs.</p> <p>In the proposed system level test methods, we utilize the loop-back</p> <p>configuration to eliminate the need for an RF instrument. The first loop-back</p> <p>test method, which is proposed for wafer level test of direct conversion</p> <p>transceivers, targets catastrophic and large parametric faults. The use of</p> <p>intermediate frequencies (IF) generates a frequency offset between the transmit</p> <p>and receive paths and prevents a direct loop-back connection. We overcome this</p> <p>problem by expanding the signal bandwidth through saturating the receive path</p> <p>composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the</p> <p>receiver path is determined, complete transceiver can be tested for catastrophic</p> <p>signal path faults by observing the output signal. A frequency spectrum</p> <p>envelope signature technique is proposed to detect large parametric faults.</p> <p>The impact of impairments, such as transmitter receiver in-phase/quadrature</p> <p>(I/Q) gain and phase mismatches on the performance have become severe due to</p> <p>high operational speeds and continuous technology scaling. In the second system</p> <p>level loop-back test method, we present BiST solutions for quadrature modulation</p> <p>transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian</p> <p>minimum shift keying (GMSK) baseband modulation schemes. The BiST methods</p> <p>use only transmitter and receiver baseband signals for test analysis. The</p> <p>mapping between transmitter input signals and receiver output signals are</p> <p>used to extract impairment and nonlinearity parameters separately with the</p> <p>help of signal processing methods and detailed nonlinear system modeling.</p> <p>The last system level test proposed in this dissertation combines the benefits </p> <p>of loop-back and multi-site test approaches. In this test method, we present </p> <p>a 2x-site test solution for RF transceivers. We perform all operations on </p> <p>communication standard-compliant signal packets, thereby putting the device </p> <p>under the normal operating conditions. The transmitter on one device under </p> <p>test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX </p> <p>path. Parameters of the two devices are decoupled from one another by carefully </p> <p>modeling the system into a known format and using signal processing techniques.</p> / Dissertation

Test strategies were developed to reduce the overall production testing cost of high-performance data converters. A static linearity testing methodology, aimed at reducing the test time of A/D converters, was developed. The architectural information of A/D converters was used, and specific codes were measured. To test a high-performance A/D converters using low-performance and low-cost test equipment a dynamic testing methodology was developed. This involved post processing of measurement data. The effect of ground bounce on accuracy of specification measurement was analyzed, and a test strategy to estimate the A/D converter specifications more accurately in presence of ground bounce noise was developed. The proposed test strategies were simulated using behavioral modeling techniques and were implemented on commercially available A/D converter devices. The hardware experiments validated the proposed test strategies. The test cost analysis was done. It suggest that a significant reduction in cost can be obtained by using the proposed test methodologies for data converter production testing.

The trend toward higher-level circuit integration is the result of demand for lower cost and smaller feature size. The goal of this trend is to have a single-chip solution, in which analog and digital circuits are placed on the same die with advanced CMOS technology. The complete integration of a system may include a digital processor, memory, ADC, DAC, signal conditioning amplifiers, frequency translation, filtering, reference voltage/current generator, etc. Although advanced fabrication technology benefits digital circuits, it poses great challenges for analog circuits. For instance, the scaling of CMOS devices degrades important analog performance such as output resistance, lowering amplifier gain. Simply lowering the power supply voltage in analog circuits does not necessarily result in lower power dissipation. The many design constraints common to the design of analog circuits makes it difficult to curb their power consumption. This is especially true for already complicated analog systems like ADCs; reducing their appetite for power requires careful analysis of system requirements and special strategies. This thesis describes a 10bits 100-MS/s low-voltage pipelined analog-to-digital converter (ADC), which consists of 8-stage-pipelined low resolution ADCs and a 2-bit flash ADC. Several critical technologies are adopted to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, folded-cascode gain-boosted amplifiers and so on. The ADC is designed in a 90nm CMOS technology with a 1.2V supply voltage.