Chiral gold complexes have been applied in homogeneous catalytic reactions since 1986, in some cases with high enantioselectivity. Acyclic diaminocarbene (ADC) ligands are acyclic analogues of N-heterocyclic carbenes (NHCs) that have larger N-CCarbene-N angles and stronger donating ability. ADCs have been developed as alternatives to phosphine and NHC ligands in homogeneous gold catalysis. In 2012, a new series of chiral gold(I) ADCs were first developed by Slaughter's group and were shown to give remarkable enantioselectivities in some reactions. Because of the hindered rotation of the N-CCarbene bonds of ADC, chiral ADC substituents can easily get close to the metal center in some conformations, although two rotameric structures are formed if the chiral amine is nonsymmetric. The selective of specific ADC conformations was the initial focus of this study. Formational selectivity of one diastereomer of an ADC ligand during synthesis was examines by measuring the relative rates of diastereomer formation in a 1H NMR kinetic study. The potential for converting multiple conformational isomers of ADCs into a single conformation, or at least a simpler mixture, was examined. This study used the analogy that anti- isomer has electronic and structural similarity with urea/thiourea, raising the possibility that 1,8-naphthyridine can be used to favor certain conformations through a self-assembled hydrogen-bonding complex. Gold(I) is a soft carbophilic Lewis acid able to active C-C π bonds to nucleophilic attack, and ADC-gold complexes are potentially useful in this regard. Therefore, biaryl gold(I) ADC complexes were examine with silver salt additives in catalytic 1,6-enyne cyclization reaction. A detailed study found that the counteranion affects the regioselectivities of these reactions more than substituents on the ancillary ADC ligands.

Scaling of CMOS to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower VDD supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower VDD environment. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The major obstacle in the VCO-based technique is linearizing the VCO voltage-to-frequency characteristic. Achieving signal-to-noise (SNR) performance better than -40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. A further challenge is implementing calibration without degrading energy efficiency performance. This thesis project discusses a complete design of a 10 bit three stage ring VCO-based ADC. A lookup-table (LUT) digital correction technique enabled by the "Split ADC" calibration approach is presented suitable for linearization of the ADC. An improvement in the calibration algorithm is introduced to ensure LUT continuity. Measured results for a 10 bit 48.8-kSps ADC show INL improvement of 10X after calibration convergence.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.

Over the past decade, there has been a growing interest in the devel- opment of integrated circuits (ICs) for wearable or implantable biosensors, aiming at providing personalized healthcare services and reducing the health-care expenses. In biosensor ICs, the analog-to-digital converter (ADC) is a key building block that acts as a bridge between analog signals and digital processors. Since most of the biosensors are attached to or implanted in hu- man bodies and powered by either portable batteries or harvested energy, ultra-low-power operation is often required. The stringent power budget im- poses challenges in designing power-efficient ADCs, especially when targeting high-resolution. Among different ADC architectures, the Sigma-Delta (Σ∆) ADC has emerged as the most suitable for low-power, high-resolution appli- cations. This thesis aims to enhance the power efficiency of continuous-time (CT) incremental Σ∆ (IΣ∆) ADCs by exploring design techniques at both architectural and circuit levels. The impact of feedback DACs in CT IΣ∆ ADCs is investigated, so as to provide power-efficient feedback DAC solutions, suitable for biosensor ap- plications. Different DAC schemes are examined analytically considering the trade-off between timing error sensitivity and power consumption. The an- alytical results are verified through behavioral simulations covering both the conventional and incremental Σ∆ modes. Additionally, by considering a typi- cal biosensor application, different feedback DACs are further compared, aim- ing to offer a reference for selecting a power-efficient DAC scheme. A two-step CT IΣ∆ ADC is proposed, analyzed, implemented and tested, with the objective of offering flexible and power-efficient A/D conversion in neural recording systems. By pipelining two CT IΣ∆ ADCs, the pro- posed ADC can achieve high-resolution without sacrificing the conversion rate. Power-efficient circuits are proposed to implement the active blocks of the proposed ADC. The feasibility and power efficiency of the two-step CT IΣ∆ ADC are validated by measurement results. Furthermore, enhancement techniques from both the architecture and circuit perspectives are discussed and implemented, which are validated by post-layout simulations. A comparative study of several CT IΣ∆ ADC architectures is presented, aiming to boost the power efficiency by reducing the number of cycles per con- version while benefiting from the advantage of CT implementation. Five CT IΣ∆ ADC architectures are analyzed and simulated to evaluate their effective- ness under ideal conditions. Based on the theoretical results, a second-order CT IΣ∆ ADC and an extended-range CT IΣ∆ ADC are selected as implemen- tation case studies together with the proposed two-step CT IΣ∆ ADC. The impact of critical circuit non-idealities is investigated. The three ADCs are then implemented and fabricated on a single chip. Experimental results reveal that the three prototype ADCs improve considerably the power efficiency of existing CT IΣ∆ ADCs while being very competitive when compared to all types of the state-of-the-art IΣ∆ ADCs. / <p>QC 20150422</p>

This thesis focuses on the design and implementation of low power Σ∆ ADCs in 130 nanometer CMOS technology. The design issues in the implementation of a third order ADC with a multi-bit and single bit quantizer are discussed. The advancement in CMOS technology has led to designing as much of electronics systems as possible with the digital circuits and digital signal processing replacing analog processing in most cases. Hence there is a need for digitizing analog signals with analog to digital converter (ADC). In communication systems this needs to be done immediately after the antenna in a receiver system. As this is difficult to implement due to high speed and high power consumption, RF signal is converted to a lower intermediate frequency (IF) and digitized. This work stresses low power implementation of high bandwidth Σ∆ ADCs for digitizing the IF. Design techniques involved in the implementation of a third order continuous time Σ∆ ADC with a 4 bit quantizer as well as a single bit quantizer for wide bandwidth are discussed. Moreover, a third order continuous time audio ADC implementation was also done. The behavioural modelling of the Σ∆ ADC along with clock jitter non-linearity model was developed and the issues in circuit design techniques are addressed. The continuous time ADCs’ major problem, namely, excess loop delay is discussed in detail and an efficient compensation technique for the same is implemented which allows a large reduction of power consumed by the ADC. Choice of loop filter architecture, quantizer and transistor level implementation are given that result in better immunity to offsets and process variations. Both the ADCs have been implemented using UMC 130 nm Mixed-mode RF-CMOS process and the simulation results for the multi-bit ADC gives a peak SNR of 56dB with a dynamic range of 65dB with power consumption of 2mW. The audio ADC achieves a peak SNR of 94.2dB with a dynamic range of 91dB.

Dans le but d’améliorer la disponibilité des services fournis par un récepteur, la conception d’un récepteur GNSS permettant de recevoir plusieurs signaux de toutes les bandes simultanément semble être la solution. Une architecture à sous échantillonnage RF optimisée de type SDR (Software Defined Radio) comportant un étage RF intégrable et reconfigurable et un étage de traitement numérique avec une implémentation logicielle du traitement en bande de base est défini pour ce récepteur GNSS, tout en répondant aux exigences des spécifications des standards GNSS : des réseaux radio cellulaires : GPS, Glonass, Galileo, Beidou. Un choix des composants discrets suite au dimensionnement system est effectué et ceci pour installer un prototype de validation expérimental. Ensuite nous nous s’intéressons à la caractérisation de la chaine RF afin d’étudier les limitations causés par la non linéarité et d’étudier la stabilité du prototype proposé. Un étage de traitement numérique des signaux IF, capturés à la sortie de l’ADC, est implémenté sous Matlab. L’acquisition de ces données permet la détermination des satellites visible à un instant donné qui nous permet éventuellement la détermination d’une position / In order to improve the availability of services provided by a receiver, designing a GNSS receiver to collect multiple signals from all bands simultaneously seems to be the solution. An optimized software-defined RF (SDR) sub-sampling architecture with an integral and reconfigurable RF stage and a digital processing stage with a software implementation of the baseband processing is defined for this GNSS receiver, while meeting the requirements GNSS standards specifications: cellular radio networks: GPS, Glonass, Galileo, Beidou. Many discrete components are selected after system dimensioning. Thus, experimental validation prototype is installed. Then we are interested in the characterization of the RF front-end in order to determine the limitations caused by the nonlinearity and to study the stability of the proposed prototype. A stage of digital processing of the IF signals, captured at the ADC output, is implemented under Matlab software. The acquisition of these data allows the determination of satellites visible at a given instant that allows us to determine a position

Målet med detta examensarbete är att undersoka om det är möjligt att reducera energiförbrukningen i ett inbyggt system m.h.a. en Field Programmable Gate Array (FPGA) med låg effektförbrukning. Genom att flytta en del funktioner från systemets Micro Controller Unit (MCU) till en FPGA, hoppas uppdragsgivaren att systemets MCU kan ges mojligheten att gå över i ett mer energisnålt sömnlage under tillräckligt långa perioder. Rapporten beskriver utvecklingsarbetet från förstudie till implementeriung och test av framtagen design i en FPGA, AGLN250 fran Microsemi. Examensarbetet har visat att det ar fullt mojligt att reducera ett inbyggt systems effektförbrukning m.h.a. en FPGA. Dock måste man, p.g.a. en FPGA:s arkitektur, vara extra aktsam pa hur designen implementeras för att effektförbrukningen inte skall bli högre än förvantat. / The purpose of this thesis is to examine the possibility of reducing an embedded system's power consumption through the use of a low-power Field Programmable Gate Array (FPGA). The customer's hope was that by relocating some of the functionality from the system's Micro Controller Unit (MCU) to an FPGA, the system's MCU could remain in its most efficient power saving mode long enough to reduce the average power consumption to an acceptable level. This paper documents the development work, from initial background material studies up to the implementation and test of suggested designs in an actual FPGA, an AGLN250 from Microsemi. The thesis work has demonstrated that it is possible to reduce the power consumption of the customer's system by relocating some of the MCU functionality to an FPGA. However, due to an FPGA's architecture, care must be taken to ensure that the design is implemented in such a way that the signal activity is reduced as far as possible. Otherwise the power consumption might end up higher than expected.

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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz. / Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz.