Amorphous oxide semiconductors are of potential interest in the display industry due to their high carrier mobility, transparency at visible wavelengths and excellent operational stability. In this dissertation, n-channel zinc-tin oxide thin-film transistors are fabricated based on a solution-based deposition approach, which allows low fabrication cost and high throughput. The effects of device configuration and process conditions on transistor performance are investigated, and circuit applications including inverters, amplifiers, and ring oscillators are demonstrated. Charge transport in the zinc-tin oxide field-effect transistors is also investigated. A transition from thermally-activated to band-like transport is observed with increasing carrier concentration in high mobility samples, which agrees well with the key predictions of the multiple trap and release model and also Mott’s mobility edge model. In addition, velocity distribution of charge carriers is studied with a time-resolved technique. This provides a more detailed picture of charge transport in field-effect transistors. P-channel organic semiconductor field-effect transistors are also investigated with a view to combine them with n-channel amorphous oxide transistors to create a hybrid organic-inorganic complementary technology. / text

Amorphous Oxide semiconductors have gained large interest in the display industry owing to their high carrier mobilities and low fabrication costs. In this thesis, n-channel solution based zinc-tin oxide (ZTO) thin-film transistors (TFTs) are studied from a circuit design perspective. The study includes an iterative process of circuit design, layout and test procedure of the fabricated devices in the lab. The device models used in circuit simulations are refined following the data fed back from each of these iterations which has enabled more accurate design of complex circuits using ZTO devices. The requirement and development of a physical compact model for performing accurate and predictive circuit simulations has been presented. The use of ZTO devices in low cost, transparent and flexible electronic applications has been investigated through the study of basic circuit blocks such as amplifiers, ring oscillators, inverters and a four stage Operational Amplifier. / text

Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued. The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom-gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation layer in such a manner that a negligible density of oxygen vacancies are present at the channel-passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter-deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution-deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual-layer passivation process does not significantly alter ZTO TFT electrical characteristics. The second focus involves creating an adaptable back-end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non-traditional and adaptable techniques. Two of the discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective. The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front-end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system. Finally, challenges associated with printing electronic materials are discussed. Organic-based solutions are easier to print due to their ability to "stick" to the substrate and form well-defined patterns, but have poor electrical characteristics due to the weakness of organic bonds. Inorganic aqueous-based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous-based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution. / Graduation date: 2013

Nanolaminate dielectrics combine two or more insulating materials in a many-layered film. These structures can be made to significantly outperform films composed of a single one of their constituent materials by adjusting the composition ratio, arrangement, and size of the component layers. In this work, atomic layer deposition (ALD) is used to fabricate pure-oxide and nanolaminate dielectrics based upon Al₂O₃ and ZrO₂. The relative performance of these dielectrics is investigated with respect to application as gate dielectrics for ZnSnO (ZTO) and InGaZnO (IGZO) amorphous-oxide-semiconductor (AOS) thin-film transistors (TFTs). AOS TFTs are promising candidates for commercial use in applications such as active-matrix displays and e-paper. It was found that the layer thickness, relative composition, and interfacial material all had an effect on TFT performance. Several variants of the Al₂O₃/ZrO₂ nanolaminate were found to exhibit superior properties to either Al₂O₃ or ZrO₂ alone. / Graduation date: 2011

Amorphous oxide semiconductors (AOSs) are of great current interest for thin-film transistor (TFT) channel layer applications. In particular, indium gallium zinc oxide (IGZO) is under intense development for commercial applications because of its demonstrated high performance at low processing temperatures. The objective of the research presented in this thesis is to provide detailed assessments of device stability, temperature dependence, and related phenomena for IGZO-based TFTs processed at temperatures between 200 °C and 300 °C. TFTs tested exhibit an almost rigid shift in log₁₀(I[subscript D]) – V[subscript GS] transfer curves in which the turn-on voltage, V[subscript ON], moves to a more positive gate voltage with increasing stress time during constant-voltage bias-stress testing of IGZO TFTs. TFT stability is improved as the post-deposition annealing temperature increases over the temperature range of 200 – 300 ºC. The turn-on voltage shift induced by constant-voltage bias-stressing is at least partially reversible; V[subscript ON] tends to recover towards its initial value of V[subscript ON] if the TFT is left unbiased in the dark for a prolonged period of time and better recovery is observed for a longer recovery period. V[subscript ON] for a TFT can be set equal to zero after bias-stress testing if the TFT electrodes are grounded and the TFT is maintained in the dark for a prolonged period of time. Attempts to accelerate the recovery process by application of a negative gate bias at elevated temperature (i.e., 100 ºC) were unsuccessful, resulting in severely degraded subthreshold swing. An almost rigid log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift to a lower (more negative) V[subscript ON] with increasing temperature is observed in the range of –50 °C to +50 °C, except for a TFT with an initial V[subscript ON] equal to zero, in which case the log₁₀(ID) – V[subscript GS] transfer curve is temperature-independent. A more detailed temperature-dependence assessment, however, indicates that the log₁₀(I[subscript D]) – V[subscript GS] transfer curve shift is not exactly rigid since the mobility is found to increase slightly with increasing temperature. A noticeable anomaly is observed in certain log₁₀(I[subscript D]) – VGS transfer curves, especially when obtained at elevated temperature (e.g., 30 and 50 ºC), in which I[subscript D] decreases precipitously near zero volts in the positive gate voltage sweep. This anomaly is attributed to a gate-voltage-step-involved detrapping and subsequent retrapping of electrons in the accumulation channel and/or channel/gate insulator interface. In fact, all IGZO TFT stability and temperature-dependence trends are attributed to channel interface and/or channel bulk trapping/detrapping. / Graduation date: 2009

<p>As  thefundamentallimits  of  two-dimensional(2D)geometric  scaling  of  commercial transistors  are  being reached,  there  is  tremendous  demand  for  new  materials  and  process innovations  that  can  keep  delivering  performance  improvements  for  future  generations  of computing chips. One major avenue being explored istheincorporation ofan increasing degree of three-dimensionality   by   vertically   stacking   logic   and   memory   layerswith   high-density interconnections.In  this  dissertation,  high-performanceultra-thin  amorphousindium  oxide transistors  are  demonstrated as  an  excellent  candidate  for these  back-end-of-line  (BEOL)  and monolithic 3D (M3D) integration applications.</p> <p>A  major  pain-point  in the  development  of  BEOL  and  M3D  systems is  the  strict  thermal budget imposed –once the bottom layer of devices is fabricated, they can generally withstand no more  than  400 °C.  It  is  exceedingly  difficult  to  directly  deposit  single-crystal  material  at  these temperatures, and polycrystalline materials will have grain boundary instability issues. Amorphous materials  generally  have  low  carrier  mobilities,  which  would  seemingly  remove  them  from contention as well. Indium oxideand itsclass of related metal oxides are exceptions. Indium oxideis  a  wide  bandgap  semiconductor  with  high  electron  mobility  up  to  about  100  cm²/V∙s  in amorphous form. Ithas a strong preference for native degenerate n-type doping which has hindered prior  devices  fabricated  with it.  In  this  dissertation,  extremely  thin  layers  on  the  order  of  1  nm thick are used for which quantum confinement effects widen the bandgap further, reliably enabling gate-controllable  carrier  densitiesand  demonstration  of  excellent  transistor  performance  with  a low thermal budget of just 225 °C.</p> <p>Detailed characterization is performed down to 40 nm channel lengths revealing excellent transistor characteristics  includingenhancement-mode operation withon currents greater than 2 A/μm, low  subthreshold  swing,and  high  on/off  ratios  due  to  the  wide  bandgap.  Subsequent chaptersdemonstrate the fundamental lower limits of off current around 6 ×10^-20A/μmby a novel measurement  technique,  good  gate  bias  stress  stability  behaviorwith  small  parameter  drift  at silicon  complementary  metal  oxide  semiconductor  (CMOS)  logic  voltages,  and  high-frequency operationin the GHz regime enabling easy operation at CMOS clock frequencies.</p>

Due to their low-temperature processing capability and ionic bonding configuration, amorphous oxide semiconductors (AOS) are well suited for applications within future mechanically flexible electronics. Over the past couple of years, amorphous zinc tin oxide (ZTO) has been proposed as indiumand gallium-free and thus more sustainable alternative to the widely deployed indium gallium zinc oxide (IGZO). The present study specifically focuses on the strain-dependence of elastic and electrical properties of amorphous zinc tin oxide thin-films sputtered at room temperature. Corresponding MESFETs have been compared regarding their operation stability under mechanical bending for radii ranging from 5 to 2 mm. Force-spectroscopic measurements yield a plastic deformation of ZTO as soon as the bending-induced strain exceeds 0.83%. However, the electrical properties of ZTO determined by Hall effect measurements at room temperature are demonstrated to be unaffected by residual compressive and tensile strain up to 1.24 %. Even for the maximum investigated tensile strain of 1.26 %, the MESFETs exhibit a reasonably consistent performance in terms of current on/off ratios between six and seven orders of magnitude, a subthreshold swing around 350 mV/dec and a field-effect mobility as high as 7.5 cm2V−1s−1. Upon gradually subjecting the transistors to higher tensile strain, the channel conductivity steadily improves and consequently, the field-effect mobility increases by nearly 80% while bending the devices around a radius of 2 mm. Further, a reversible threshold voltage shift of about −150 mV with increasing strain is observable. Overall, amorphous ZTO provides reasonably stable electrical properties and device performance for bending-induced tensile strain up to at least 1.26% and thus represent a promising material of choice considering novel bendable and transparent electronics.

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this thesis. Within this theme, three primary areas of focus are pursued. The first focus is the realization of a transparent three-stage ring oscillator with buffered output and an output frequency in the megahertz range. This leads to the possibility of transparent radio frequency applications, such as transparent RFID tags. At the time of its fabrication, this ring oscillator was the fastest oxide electronics ring oscillator reported, with an output frequency of 2.16 MHz, and a time delay per stage of 77 ns. The second focus is to ascertain whether a three-terminal device (i.e., a TFT) is an appropriate structure for conducting space-charge-limited-current (SCLC) measurements. It is found that it is not appropriate to use a diode-tied or gate-biased TFT configuration for conducting a SCLC assessment since square-law theory shows that transistor action alone gives rise to I proportional to V² characteristics, which can easily be mistakenly attributed to a SCLC mechanism. Instead, a floating gate TFT configuration is recommended for accomplishing SCLC assessment of AOS channel layers. The final focus of this work is to describe an assessment procedure appropriate for determining if a dielectric is suitable for use as a TFT gate insulator. This is accomplished by examining the shape of a MIM capacitor's log(J)-ξ curve, where J is the measured current density and ξ is the applied electric field. An appropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that expresses a clear breakover knee, indicating a high-field conduction mechanism dominated by Fowler-Nordheim tunneling. Such a dielectric produces a TFT with a minimal gate leakage which does not track with the drain current in a log(I[subscript D])-V[subscript GS] transfer curve. An inappropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that does not express a clear breakover knee, indicating that the dominate conduction mechanism is defect driven (i.e., pin-hole like shunt paths) and, therefore, the dielectric is leaky. It is shown that experimental log(J)-ξ leakage curves can be accurately simulated using Ohmic, space-charge-limited current (SCLC), and Fowler-Nordheim tunneling conduction mechanisms. / Graduation date: 2010