For the first method, a novel linearization scheme for CMOS double-balanced mixer based on the use of multi-bias dual-gate transistors is presented. In this technique, two intermodulation distortion components with proper phase relationship, generated by devices operating at different bias conditions, are added together to cancel each other for the improvement of mixer's linearity. The measured performance of a fabricated CMOS mixer operating at RF frequency of 2.45GHz and LO frequency of 2.35GHz is demonstrated. Over 35dB of IMD reduction is achieved by the proposed method under optimal biasing condition. / In the second design, a novel linearization scheme for cascode amplifier based upon capacitive feedback is presented. This method involves the optimal design of the feedback network for IMD reduction. By using Volterra series analysis, expression for IMD products is derived and the corresponding circuit parameters for optimized linearity are obtained. For experimental verification, CMOS cascode amplifiers are designed and fabricated to operate at 2.45GHz with supply voltage of 2V. By measurement, IIP3 is improved of almost 7dB by using the proposed feedback technique. The performance dependency of the fabricated amplifiers under different bias conditions is also examined. The results indicate that the proposed technique can offer low sensitivity to the variation of process parameters. / Linearity is one of the major requirements in modern communication systems due to the limited channel spacing. In the past years, various linearization schemes have been studied extensively for RF circuit design such as low-noise amplifiers and power amplifiers. These techniques offer IMD reduction at the expense of circuit complexity. In the last decade, much effort has been devoted to the development of single-chip RF transceiver using sub-micron CMOS technology. This thesis presents three simple and effective linearization techniques for CMOS mixer and amplifier design. They are experimentally verified by circuit fabrication based on 0.35mum CMOS process. / The last approach combines the advantages of source degeneration and the capacitive feedback for cascode amplifier linearization. Experiments are performed on CMOS amplifiers operating at 2.45GHz, and more than 11dB of IIP3 enhancement is observed. / Au Yeung, Chung Fai. / "August 2007." / Adviser: Chang Kwok Keung. / Source: Dissertation Abstracts International, Volume: 69-02, Section: B, page: 1189. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (p. 153-161). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract in English and Chinese. / School code: 1307.

Hon Kwok-Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1. --- System Architecture --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Receiver Architectures --- p.2 / Chapter 1.2.1 --- Superheterodyne Receiver --- p.2 / Chapter 1.2.2 --- Homodyne Receiver --- p.3 / Chapter 1.2.3 --- Image-Reject Receiver --- p.5 / Chapter 1.2.4 --- Low intermediate frequency Receiver --- p.7 / Chapter 1.3 --- Double Intermediate Frequency Receivers --- p.8 / Chapter 1.3.1 --- Introduction --- p.8 / Chapter 1.3.2 --- Background Theory --- p.8 / Chapter 2. --- Receiver Fundamentals --- p.23 / Chapter 2.1 --- Noise model --- p.23 / Chapter 2.1.1 --- Thermal noise of resistors --- p.23 / Chapter 2.1.2 --- Channel noise of transistors --- p.24 / Chapter 2.2 --- Noise Figure --- p.26 / Chapter 2.3 --- Linearity --- p.26 / Chapter 2.3.1 --- 1 -dB Compression point --- p.27 / Chapter 2.3.2 --- Third Intercept point (IP3) --- p.28 / Chapter 2.3.3 --- Dynamic Range (DR) --- p.30 / Chapter 2.3.3.1 --- Spurious-Free Dynamic Range (SFDR) --- p.30 / Chapter 2.3.3.2 --- Blocking Dynamic Range (BDR) --- p.32 / Chapter 3. --- Spiral Inductor --- p.33 / Chapter 3.1 --- Spiral inductor modeling --- p.34 / Chapter 3.2 --- Spiral Inductor model parameters --- p.36 / Chapter 3.3 --- Characteristic of spiral inductor --- p.36 / Chapter 3.4 --- Inductor Design and Optimization --- p.37 / Chapter 4. --- Low Noise Amplifier (LNA) --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Common LNA Architectures --- p.39 / Chapter 4.2.1 --- Resistive Termination --- p.39 / Chapter 4.2.2 --- 1/gm Termination --- p.42 / Chapter 4.2.3 --- Shunt-Series Feedback --- p.43 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.43 / Chapter 4.3 --- Full Schematic diagram of the Low Noise Amplifier --- p.45 / Chapter 4.4 --- Full noise analysis of the LNA using inductive source degeneration --- p.46 / Chapter 4.4.1 --- Output noise due to channel noise --- p.46 / Chapter 4.4.1.1 --- Output noise due to i2d --- p.47 / Chapter 4.4.1.2 --- "Output noise due to i2g,u" --- p.47 / Chapter 4.4.1.3 --- "Output noise due to i2g,c and i2d" --- p.49 / Chapter 4.4.2 --- "Output noise due to Rg R,l Rs" --- p.51 / Chapter 4.4.3 --- Noise factor calculation --- p.52 / Chapter 4.4.3.1 --- Rl calculation --- p.52 / Chapter 4.4.3.2 --- Rg calculation --- p.52 / Chapter 4.4.3.3 --- Ql calculation --- p.53 / Chapter 4.4.3.4 --- wT calculation --- p.53 / Chapter 4.4.3.5 --- x calculation --- p.53 / Chapter 4.5 --- Simulation Result of the low noise amplifier (100 finger gate poly) --- p.54 / Chapter 4.5 --- Experimental Result of the low noise amplifier (100 finger gate poly) --- p.56 / Chapter 5. --- Down-conversion Mixer --- p.58 / Chapter 5.1 --- Introduction --- p.58 / Chapter 5.2 --- Gilbert Cell Mixer --- p.59 / Chapter 5.2.1 --- Circuit Description --- p.59 / Chapter 5.2.2 --- Basic Operation --- p.60 / Chapter 5.2.3 --- Simulation Result of the Gilbert Cell Mixer --- p.62 / Chapter 5.3 --- Single-ended to Differential-ended Converter --- p.66 / Chapter 5.3.1 --- Simulation Result of the Single-Ended to Differential-Ended Converter --- p.68 / Chapter 5.4 --- Experimental Result of The Gilbert Cell Mixer --- p.70 / Chapter 5.4.1 --- 1-dB compression point experiment --- p.70 / Chapter 5.4.2 --- IIP3 experimental setup and result --- p.72 / Chapter 5.4.3 --- "Experimental result of 1 -dB compression point, IIP3, conversion gain, SFDR and BDR" --- p.74 / Chapter 5.4.4 --- LO power verse conversion gain --- p.75 / Chapter 5.4.5 --- Intermediate frequency verse conversion gain --- p.77 / Chapter 5.4.6 --- Experimental result of input matching and isolation --- p.78 / Chapter 6. --- Asymmetric Polyphase Network --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Performance of the Asymmetric Polyphase Network --- p.81 / Chapter 6.2.1 --- First Building Block --- p.82 / Chapter 6.2.2 --- Second Building Block --- p.83 / Chapter 6.2.3 --- Third Building Block --- p.84 / Chapter 6.2.4 --- Forth Building Block --- p.84 / Chapter 6.3 --- Simulation result of the asymmetric polyphase network --- p.85 / Chapter 6.4 --- Experimental result of the asymmetric polyphase network --- p.86 / Chapter 7. --- Conclusion --- p.87 / Chapter 8. --- Reference --- p.89 / Chapter 9. --- Appendix A --- p.92 / Chapter 10. --- Appendix B --- p.95 / Chapter 11. --- Appendix C --- p.98 / Chapter 12. --- Appendix D --- p.99

The miniaturization of electronics is a technique that holds a lot of potential in improving system performance in a variety of applications. The simultaneous miniaturization of sensors into the nano-scale has provided new ways to probe biological systems. Careful co-design of these electronics and sensors can unlock measurements and experiments that would otherwise be impossible to achieve. This thesis describes the design of two such instrumentation amplifiers and shows that significant gains in temporal resolution and noise performance are possible through careful optimization. A custom integrated amplifier is developed for improving the temporal resolution in nanopore recordings. The amplifier is designed in a commercial 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. A platform is then built with the amplifier at its core that integrates glass-passivated solid-state nanopores to achieve measurement bandwidth over an order of magnitude greater than the state of the art. The use of wavelet transforms for denoising the data and further improving the signal-to-noise ratio (SNR) is then explored. A second amplifier is designed in a 0.18 μm CMOS process for intracellular recordings from neurons. The amplifier contains all the compensation circuitry required for canceling the effects of the electrode non-idealities. Compared to equivalent commercial systems and the state of the art, the amplifier performs comparably or better while consuming orders of magnitude lower power. These systems can inform the design of extremely miniaturized application-specific integrated amplifiers of the future.

Tsang, Ka Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract / Acknowledgement / Content / Chapter 1. --- Introduction / Chapter 1.1 --- Motivation for Current-Mode Circuit --- p.1-1 / Chapter 1.2 --- Basic Current-Mode Building Block --- p.1-3 / Chapter 1.3 --- Adjoint Principle --- p.1-5 / Chapter 1.4 --- Characteristics of Current Amplifier --- p.1-8 / Chapter 1.5 --- Application of Current-Mode Circuit --- p.1-10 / Chapter 2. --- Conventional Design / Chapter 2.1 --- System Overview --- p.2-1 / Chapter 2.2 --- First Architecture and Circuit (Fully Current Mode) --- p.2-6 / Chapter 2.3 --- Second Architecture and Circuit (Voltage Mode) --- p.2-10 / Chapter 2.4 --- Performance Indicator --- p.2-15 / Chapter 3. --- Proposed Design / Chapter 3.1 --- Design Motivation --- p.3-1 / Chapter 3.2 --- Saturation Voltage Gain Stage (SVGS) --- p.3-7 / Chapter 3.3 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) --- p.3-13 / Chapter 3.4 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) --- p.3-22 / Chapter 4. --- IC Measurement / Chapter 5. --- Conclusion / Chapter 5.1 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) over Conventional Design --- p.5-1 / Chapter 5.2 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) over Conventional Design --- p.5-2 / Chapter 6. --- Future Idea / Chapter 7. --- Reference / Chapter 8. --- Appendix

Biopotential amplifiers and DC amplifiers in general play an important role in neurophysiological research and modern medical practice. This thesis investigates the application of recent semi-conductor technology to the design of a high-performance amplifier for EEG, EKG, and EMG. This amplifier can also be used with low-level transducers. In particular, the performance of a BJT OP AMP version is compared with that of an amplifier utilizing FET OP AMPS.Ball State UniversityMuncie, IN 47306

High-efficiency performance is one of the most important requirements of power amplifiers (PAs) for wireless applications. However, the design of highly efficient CMOS PAs for watt-level applications is a challenging task. This dissertation focuses on the development of the design method for highly efficient CMOS PAs to overcome the fundamental difficulties presented by CMOS technology. In this dissertation, the design method and analysis for a high-power and highefficiency class-E CMOS PA with a fully integrated transformer have been presented. This work is the first effort to set up a comprehensive design methodology for a fully integrated class-E CMOS PA including effects of an integrated transformer, which is very crucial for watt-level power applications. In addition, to improve efficiency of cascode class-E CMOS PAs, a charging acceleration technique is developed. The method accelerates a charging speed to turn off the common-gate device in the off-state, thus reducing the power loss. To demonstrate the proposed cascode class-E PA, a prototype CMOS PA was implemented in a 0.18-μm CMOS process. Measurements show an improvement of approximately 6% in the power added efficiency. The proposed cascode class-E PA structure is suitable for the design of high-efficiency class-E PAs while it reduces the voltage stress across the device.

There have been many efforts to improve efficiency of transmitter while meeting stringent linearity requirement of modern communication system. Among the technology to enhance efficiency of linear transmitter, the out-phasing technologies, also called the linear amplification with nonlinear components (LINC), is considered as a promising technology. LINC has been studied long times, since it provides excellent linearity with high efficiency by allowing adopt high efficient switch-mode power amplifiers. However, The LINC transmitter has some technical challenges: linearity degradation due to amplitude and phase mismatches, efficiency degradation due to poor combining efficiency, and narrow frequency bandwidth due to output matching network of switching power amplifier. In this thesis, some state-of-the-art techniques for solving the problems of LINC transmitters are presented. An unbalanced phase calibration technique compensates amplitude/phase mismatches between two parallel paths in the LINC system, and multi-level LINC (MLINC) and an uneven multi-level LINC (UMLINC) structure improve the overall power efficiency. And the reconfigurable Class-D switching PA enables multi-band operation with high efficiency and good linearity. With these techniques, the new multi-band out-phasing transmitter improves the efficiency without sacrificing the linearity performance.

Thesis (Ph. D.)--University of Hong Kong, 2010. / Includes bibliographical references (leaves 138-149). Also available in print.

Thesis (Ph. D.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2004. / Includes bibliographical references (p. 153-158).

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 169-175). Also available in electronic format on the Internet.