Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de se reduzir o consumo de energia dos circuitos. Partiu-se dos antigos 5 V, padrão estabelecido pela lógica TTL nos anos 70, até os circuitos modernos que operam com alimentação pouco abaixo de 1 V. Entretanto, desde os primeiros anos da década de 2000, a tensão de alimentação está estabilizada neste patamar, devido a limitações tecnológicas que tem se mostrado difíceis de serem transpostas. Tal desafio tem sido estudado por grupos de pesquisa ao redor do mundo, e diversas estratégias tem sido propostas para se chegar a circuitos analógicos e digitais que operem sob tensão de alimentação bem inferior a 1 V. De fato estes grupos têm focado seus estudos em circuitos que operam com tensão de alimentação inferior a 0,5 V, alguns chegando à casa de 200 ou 100 mV, ou até menor. Dentre as diversas classes de circuitos, os conversores de dados dos tipos digital-analógico (DAC) e analógicodigital (ADC) são circuitos fundamentais ao processo de integração entre os módulos que processam sinais analogicamente e os que processam sinais digitalmente, sendo assim essenciais à implementação dos complexos SoCs (System-on-Chips) da atualidade. Este trabalho apresenta um estudo sobre o desempenho da configuração MOSFET em rede M-2M (similar à rede R-2R que emprega resistores), utilizada como circuito conversor digital-analógico, quando dimensionada para operar sob tensão de alimentação muito baixa, da ordem de 200 mV ou inferior. Tal estudo se baseia no emprego de um modelo para os MOSFETs que é contínuo desde a condição de inversão fraca (subthreshold) até a inversão forte, e inclui o uso de um modelo de descasamento entre MOSFETs que é válido para qualquer condição de operação. Com base neste estudo foi desenvolvida uma metodologia de projeto, capaz de estabelecer as relações de compromisso entre “tensão de alimentação”, “resolução efetiva” e “área ocupada em silício”, fundamentais para se atingir um circuito otimizado. Resultados de simulação elétrica são apresentados e confrontados com os resultados analíticos, visando a comprovação da metodologia. O circuito já foi enviado para fabricação, e deve começar a ser testado em breve.

This work deals with the digital to analog converter. Technology used for this proposal is ON SEMICONDUCTOR CMOS07 utilizing Cadence design software. The work presents different blocks of the converter, especially the compensation of the amplifier input voltage offset and a reference voltage source.

This thesis work consists of two research projects. The first project presented is on waveform design for car radars. These radars are used to detect other vehicles to avoid collision. In this project, we attempt to find the best waveform that distinguishes large objects from small ones. This helps the radar system reach more reliable decisions. We consider several models of the problem with varying complexity. For each model, we present optimization results calculated under various constraints regarding how the waveform is generated and how the reflected signal is processed. The results show that changing the radar waveform can result in better target classification. The second project is about digital-to-analog converter (DAC) linearization. Ideally, DACs have a linear input-output relation. In practice, however, this relation is nonlinear which may be harmful for many applications. A more linear input-output relation can be achieved by modifying the input to a DAC. This method, called predistortion, requires a good understanding of how DAC errors contribute to the nonlinearity. Assuming a simple DAC model, we investigate how different error functions lead to different types of nonlinearities through theoretical analyses and supporting computer simulations. We present our results in terms of frequency spectrum calculations. We show that the nonlinearity observed at the output strongly depends on how the error is modeled. These results are helpful in designing a predistorter for linearization.

No description available.

<p>The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.</p><p>The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.</p>

A 4 bit, Rom-Less Direct Digital Frequency Synthesizer (DDFS) is designed in 65nm CMOS technology. Interleaving with Return-to-Zero (RTZ) technique is used to increase the output bandwidth and synthesized frequencies. The performance of the designed synthesizer is evaluated using Cadence Virtuoso design tool. With 3.2 GHz sampling frequency, the DDFS achieves the spurious-free dynamic range (SFDR) of 60 dB to 58 dB for synthesized frequencies between 200 MHz to 1.6 GHz. With 6.4 GHz sampling frequency, the synthesizer achieves the SFDR of 46 dB to 40 dB for synthesized frequencies between 400 MHz to 3.2 GHz. The power consumption is 80 mW for the designed mixed-signal blocks.

The Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost. The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.

With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.

No description available.

In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been proven to provide low power and high speed operation. Typically, capacitor matching is the best among all integrated circuit components but the mismatch among nominally equal value capacitors will introduce nonlinear distortion. By using dynamic element matching (DEM) technique in the MSB DAC, the nonlinearity caused by capacitor mismatch is greatly reduced. The output buffer employed direct charge transfer (DCT) technique that can minimize kT/C noise without increasing the power dissipation. This segmented DAC is designed and simulated in 0.18 μm CMOS technology, and the simulated core DAC block only consumes 403 μW. / Graduation date: 2012