Continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ΔΣ ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ΔΣ ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18μm BiCMOS process.

Recently, smart dust or wireless sensor networks are gaining more attention.These autonomous, ultra-low power sensor-based electronic devices sense and process burst-type environmental variations and pass the data from one node (mote) to another in an ad-hoc network. Subsystems for smart dust are typically the analog interface (AI), analog-to-digital converter (ADC), digital signal processor (DSP), digital-to-analog converter (DAC), power management, and transceiver for communication. This thesis project describes an event-driven (ED) digital signal processing system (ADC, DSP and DAC) operating in continuous-time (CT) with smart dust as the target application. The benefits of the CT system compared to its conventional counterpart are lower in-band quantization noise and no requirement of a clock generator and anti-aliasing filter, which makes it suitable for processing burst-type data signals. A clockless EDADC system based on a CT delta modulation (DM) technique is presented. The ADC output is digital data, continuous in time, known as “data token”. The ADC employs an unbuffered, area efficient, segmented resistor-string (R-string) feedback DAC. A study of different segmented R-string DAC architectures is presented. A comparison in component reduction with prior art shows nearly 87.5% reduction of resistors and switches in the DAC and the D flip-flops in the bidirectional shift registers for an 8-bit ADC, utilizing the proposed segmented DAC architecture. The obtained SNDR for the 3-bit, 4-bit and 8-bit ADC system is 22.696 dB, 30.435 dB and 55.73 dB, respectively, with the band of interest as 220.5 kHz. The CTDSP operates asynchronously and process the data token obtained from the EDADC. A clockless transversal direct-form finite impulse response (FIR) low-pass filter (LPF) is designed. Systematic top-down test-driven methodology is employed through out the project. Initially, MATLAB models are used to compare the CT systems with the sampled systems. The complete CTDSP system is implemented in Cadence design environment. The thesis has resulted in two conference contributions. One for the 20th European Conference on Circuit Theory and Design, ECCTD’11 and the other for the 19th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC’11. We obtained the second-best student paper award at the ECCTD.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

The programmability property of floating-gate transistors is exploited in this work to compensate for mismatch and device parameter variations in various high performance analog circuits. A careful look is taken at the characteristics and behavior of floating-gate transistors; issues such as programming, precision, accuracy, and charge retention are addressed. An alternate approach to reduce the offset voltage of the amplifier is presented. The proposed approach uses floating-gate transistors as programmable current sources that provide offset compensation while being a part of the amplifier of interest during normal operation. This results in an offset voltage cancelation that is independent of other amplifier parameters and does not dissipate additional power. Two compact programmable architectures that implement a voltage reference based on the charge difference between two floating-gate transistors are introduced. The references exhibit a low temperature coefficient (TC) as all the transistors temperature dependencies are canceled. Programming the charge on the floating-gate transistors provides the flexibility of an arbitrary accurate voltage reference with a single design and allows for a high initial accuracy of the reference. Also, this work presents a novel programmable temperature compensated current reference. The proposed circuit achieves a first order temperature compensation by canceling the negative TC of an on-chip poly resistor with the positive TC of a MOS transistor operating in the ohmic region. Programmability of the ohmic resistor enables optimal temperature compensation while programmability of the reference voltage allows for an accurate current reference for a wide range of values. Finally, this work combines the already established DAC design techniques with floating-gate circuits to obtain a high precision converter. This approach enables higher accuracy along with a substantial decrease of the die size.

Today&amp / #8217 / s analog modulators and upconverters are inadequate to synthesize and modulate signals with high &amp / #8216 / Spurious Free Dynamic Range&amp / #8217 / (SFDR). Thus, the main objective of this thesis is to design and implement a &amp / #8216 / Digital Signal Synthesizer&amp / #8217 / (DSS) that is capable of synthesizing signals between 50-100 MHz with 60dB SFDR and to modulate them variable symbol rates and modulation techniques with very high phase/frequency resolution and switching speed while keeping the amplitude modulation occurring during a modulated symbol duration as small as possible. In this thesis, digital words of the desired signals are first synthesized in a &amp / #8216 / Field Programmable Gate Array&amp / #8217 / (FPGA) using &amp / #8216 / Direct Digital Synthesizer&amp / #8217 / (DDS) fundamentals and then converted to analog signals with a high speed &amp / #8216 / Digital to Analog Converter&amp / #8217 / (DAC). In order to attain the analog requirements, the system variables such as DAC analog performance, nonlinearities, sample and hold affects, DDS parameters, system clock, bandwidth requirements of analog filters and how they effect the output performance are studied. FPGA blocks that are capable of modulating and synthesizing desired signals are designed and programmed on a FPGA. Finally, single tone and modulated signals are synthesized with this DSS implementation and measured in order to verify this system&amp / #8217 / s performance and capabilities.

Commercialization of infrared (IR) vision is of vital importance for many applications, such as automobile and health care. The main obstacle in front of the further spread of this technology is the high price. The cost reduction is achieved by placing on-chip electronics and diminishing the camera size, where one of the important components is the analog-to-digital converter (ADC). This thesis reports the design of a successive approximation register (SAR) ADC for low-cost microbolometers and its test electronics. Imaging ADCs are optimized only for the specific application in order to achieve the lowest power, yet the highest performance. The successive approximation architecture is chosen, due to its low-power, small-area nature, high resolution potential, and the achievable speed, as the ADC needs to support a 160x120 imager at a frame rate of 25 frames/sec (fps). The resolution of the ADC is 14 bit at a sampling rate of 700 Ksample/sec (Ksps). The noise level is at the order of 1.3 LSBs. The true resolution of the ADC is set to be higher than the need of the current low-cost microbolometers, so that it is not the limiting factor for the overall noise specifications. The design is made using a 0.18&micro / m CMOS process, for easy porting of design to the next generation low-cost microbolometers. An optional dual buffer approach is used for improved linearity, a modified, resistive digital-to-analog converter (DAC) is used for enhanced digital correction, and a highly configurable digital controller is designed for on-silicon modification of the device. Also, a secondary 16-bit high performance ADC with the same topology is designed in this thesis. The target of the high resolution ADC is low speed sensors, such as temperature sensors or very small array sizes of infrared sensors. Both of the SAR ADCs are designed without switched capacitor circuits, the operation speed can be minimized as low as DC if an extremely low power operation is required. A compact test setup is designed and implemented for the ADC. It consists of a custom designed proximity card, an FPGA card, and a PC. The proximity card is designed for high resolution ADC testing and includes all analog utilities such as voltage references, voltage regulators, digital buffers, high resolution DACs for reference generation, voltage buffers, and a very high resolution &Delta / -&Sigma / DAC for input voltage generation. The proximity card is fabricated and supports automated tests, because many components surrounding the ADC are digitally controllable. The FPGA card is selected as a commercially available card with USB control. The full chip functionalities and performances of both ADCs are simulated. The complete layouts of both versions are finished and submitted to the foundry. The ADC prototypes consist of more than 7500 transistors including the digital circuitry. The power dissipation of the 16-bit ADC is around 10mW, where the 14-bit device consumes 30mW. Each of the dies is 1mm x 5mm, whereas the active circuits occupy around 0.5mm x 1.5mm silicon area. These chips are the first steps in METU for the realization of the digital-in digital-out low cost microbolometers and low cost sensors.

Στην παρούσα Διπλωματική Εργασία μελετάται η δομή και τα χαρακτηριστικά ενός νέου μετατροπέα ψηφιακού σήματος σε αναλογικό (Digital to Analog Converter DAC). Η δομή του DAC βασίζεται στη γνωστή δομή του συμβατικού R2R Ladder και θα μπορούσε να θεωρηθεί σαν μία δισδιάστατη ανάπτυξη του Ladder. Αυτό σημαίνει ότι η νέα μορφή του DAC χρησιμοποιεί σαφώς περισσότερες αντιστάσεις από τον συμβατικό Ladder, όμως δίνεται η δυνατότητα της ρύθμισης του ρεύματος εξόδου του κάθε κλάδου. Αυτό έχει ως συνέπεια τη δραματική βελτίωση της γραμμικότητας του DAC. Επιπλέον στην Εργασία αυτή μελετήθηκαν με χρήση της θεωρίας των πιθανοτήτων τα χαρακτηριστικά του απλού Ladder και χρησιμοποιήθηκαν για την εξαγωγή συμπερασμάτων που αφορούν στη γραμμικότητα της νέας δομής Ladder. Τα θεωρητικά αποτελέσματα επιβεβαιώθηκαν με εξομοιώσεις. Τέλος, μία σχεδίαση σε φυσικό επίπεδο με την χρήση μόνο MOSFETS και CMOS τεχνολογίας (χωρίς την χρήση αντιστάσεων) σχεδιάσθηκε και εξομοιώθηκε στο Cadence ένας Ladder της νέας δομής. / This Diploma Thesis studies on a new Digital to Analog Converter (DAC) structure developed in the Applied Electronics Laboratory of the University of Patras. The new DAC structure is based on the simple R2R ladder combining several of them in a 2-dimentional grid. As result a high linearity DAC is derived after a simple calibration procedure. The Diploma Thesis presents results on probability of the simple R2R Ladder, employs these results so as to forecast the linearity of the 2-dimentional Ladder, whereas confirms theoretical results with simulations. Finally, a DAC based on the 2-dimentional topology has been designed and simulated using Cadence, in the framework of this Diploma Thesis.

Submitted by Lucienne Costa (lucienneferreira@ufcg.edu.br) on 2018-05-23T00:02:18Z No. of bitstreams: 1 VANDERSON DE LIMA REIS – TESE (PPGEE) 2017.pdf: 6102324 bytes, checksum: 3f5467799d6127fee0e2bce02ef9d841 (MD5) / Made available in DSpace on 2018-05-23T00:02:18Z (GMT). No. of bitstreams: 1 VANDERSON DE LIMA REIS – TESE (PPGEE) 2017.pdf: 6102324 bytes, checksum: 3f5467799d6127fee0e2bce02ef9d841 (MD5) Previous issue date: 2017-04-20 / Capes / Nos conversores Analógicos Digitais (ADC) com frequência de conversão baseada no Teorema de Nyquist, o parâmetro básico para orientar a aquisição é a largura de banda do sinal. O tratamento da informação e a remoção da redundância são realizados após a representação digital obtida do sinal. A Amostragem Compressiva foi proposta como uma técnica de digitalização que explora a esparsidade do sinal em um determinado domínio, para capturar apenas seu conteúdo de informação, com uma taxa que pode ser menor do que a preconizada pelo Teorema de Nyquist. As arquiteturas em hardware para implementar a Amostragem Compressiva são chamadas de Conversores Analógicos para Informação (AIC). Os AIC propostos na bibliografia exploram a esparsidade do sinal em um determinado domínio, e por isso cada arquitetura é especifica para uma classe de sinais. Nesta tese propõe-se um AIC configurável, baseado em arquiteturas conhecidas, capaz de adquirir sinais de várias classes, alterando seus parâmetros de configuração. No trabalho desenvolveu-se um modelo computacional, que permite analisar o comportamento dinâmico do AIC, e dos parâmetros de hardware propostos, bem como foi feita a implementação física da arquitetura proposta. Verificou-se a adaptabilidade dessa arquitetura a partir dos resultados obtidos, pois foi possível fazer a aquisição de mais de uma classe de sinais. / In analog-to-digital converters (ADC) based on Nyquist Theorem, the basic parameter to guide acquisition is the bandwidth of the signal. The information processing and redundancy removal are performed after the digital representation obtained from the signal. Compressed Sensing was proposed as a digitalization technique that exploits the sparsity of the signal in a given domain to capture only its information content, at a rate that may be lower than that advocated by the Nyquist Theorem. The hardware architectures to implement Compressed Sensing are called Analog to Information Converters (AIC). The AICs proposed in the bibliography exploit the sparsity of the signal in a given domain, and therefore each architecture is specific for a class of signals. This thesis proposes a configurable AIC, based on known architectures, capable of acquiring signals from several classes, changing its configuration parameters. A computational model was developed to analyze the dynamic behavior of AIC and proposed hardware parameters, as well as the physical implementation of the proposed architecture. It was verified the adaptability of the proposed architecture from the obtained results, since it was possible to perform the acquisition of more than one class of signals.

High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.

The subject of this thesis is design and construction of a periodic signal generator prototype. The generator will use Atmel XMEGA128A4U microcontroller with computer control managed via USB interface. The thesis contains general solutions to the problem of generating signals with a special focus on utilization of DA converter – digital synthesis and reconstruction of the signal from DA converter output to continuous signal. The thesis further deals with implementation of the USB layer using two libraries (LUFA library on microcontroller side and LubUsbDotNet library on computer side). The final solution will include DC step-up converter for signal peak amplitude assessment and summing amplifier for adding the DC voltage to the output signal. The application will allow for generating signals of various shapes including user-defined ones. These signals will be displayed in the actual application window. There, users will be allowed to create user-defined signal in easy-to-use GUI or load it directly from a file.