Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquence. / This thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation.

To explore spectral opportunities in wideband regime for cognitive radio we need a wideband spectrum sensing receiver. Current wideband receiver architectures need wideband analog to digital converter (ADC) to sample wideband signal. As current state-of-art ADC has limitation in terms of power and sampling rate, we need to explore some alternative solutions. Compressive sampling (CS) data acquisition method is one of the solutions. Cognitive Radio signal, which is sparse in frequency domain can be sampled at Sub-Nyquist rate using low rate ADC. To relax the receiver complexity in terms of performance requirement we can use Modulated Wideband Converter (MWC) architecture, a Sub-Nyquist sampling method. In this thesis circuit design of this architecture covers signal within a frequency range of 500 MHz to 2.1 GHz, with a channel bandwidth of 1600 MHz. By using 8 parallel lines with channel trading factor of 11, effective sampling rate of 550 MHz is achieved for successful support recovery of multi-band input signal of size N=12.

This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Le sujet de cette thèse est de concevoir un prototype de capteur à pixel CMOS adapté aux couches extérieures du détecteur de vertex de l'International Linear Collider (ILC).Il est le premier prototype de capteur CMOS intégrant un ADC en bas de colonne de 4-bit et une matrice de pixels, dédié aux couches externes. L'architecture du prototype nommé MIMOSA 31 comprend une matrice de pixels de 48 colonnes par 64 lignes, des ADC en bas de colonne. Les pixels sont lus ligne par ligne en mode d'obturation roulant. Les ADCs reçoivent la sortie des pixels en parallèle achève réalisent la conversion en effectuant une approximation de multi-bit/step. Sachant que dans les couches externes de l'ILC, la densité de pixels touchés est de l'ordre de quelques pour mille, !'ADC est conçu pour fonctionner en deux modes (actifs et inactifs) afin de minimiser la consommation d'énergie. Les résultats indiquent que MIMOSA 31 répond aux performances nécessaires pour cette couche de capteurs. / This work deals with the design of a CMOS pixel sensor prototype (called MIMOSA 31) for the outer layers of the International Linear Collider (ILC) vertex detector. CMOS pixel sensors (CPS) also called monolithic active pixel sensors (MAPS) have demonstrated attractive performance towards the requirements of the vertex detector of the future linear collider. MIMOSA 31developed at IPHC-Strasbourg is the first pixel sensor integrated with 4-bit column-level ADC for the outer layers. It is composed of a matrix of 64 rows and 48 columns. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). At the bottom of the pixel array, each column is terminated with an analog to digital converter (ADC). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector, the hit density is inthe order of a few per thousand, this ADC works in two modes: active mode and inactive mode. This thesis presents the details of the prototype chip and its laboratory test results.

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has driven the need for electronic store cord neural signals from many neurons. The continuous increase in demand of data from more number of neurons is challenging for the design of an efficient neural recording frontend(NRFE). Power consumption per channel and data rate minimization are two key problems which need to be addressed by next generation of neural recording systems. Area consumption per channel must be low for small implant size. Dynamic range in NRFE can vary with time due to change in electrode-neuron distance or background noise which demands adaptability. In this thesis, techniques to reduce power-per-channel and area-per-channel in a NRFE, via new circuits and architectures, are proposed. An area efficient low power neural LNA is presented in UMC 0.13 μm 1P8M CMOS technology. The amplifier can be biased adaptively from 200 nA to 2 μA , modulating input referred noise from 9.92 μV to 3.9μV . We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier. It obviates the need of large input coupling capacitance in the amplifier which saves considerable amount of chip area. In vitro experiments were performed to validate the applicability of the neural LNA in neural recording systems. ADC is another important block in a NRFE. An 8-bit SAR ADC along with the input and reference buffer is implemented in 0.13 μm CMOS technology. The use of ping-pong input sampling is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the output data rate, the A/D process is only enabled through a proposed activity dependent A/D scheme which ensures that the background noise is not processed. Based on the dynamic range requirement, the ADC resolution is adjusted from 8 to 1 bit at 1 bit step to reduce power consumption linearly. The ADC consumes 8.8 μW from1Vsupply at1MS/s and achieves ENOB of 7.7 bit. The ADC achieves FoM of 42.3 fJ/conversion in 0.13 μm CMOS technology. Power consumption in SARADCs is greatly benefited by CMOS scaling due to its highly digital nature. However the power consumption in the capacitive DAC does not scale as well as the digital logic. In this thesis, two energy-efficient DAC switching techniques, Flip DAC and Quaternary capacitor switching, are proposed to reduce their energy consumption. Using these techniques, the energy consumption in the DAC can be reduced by 37 % and 42.5 % compared to the present state-of-the-art. A novel concept of code-independent energy consumption is introduced and emphasized. It mitigates energy consumption degradation with small input signal dynamic range.

Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range. / <p>QC 20170905</p>

With the rapid development of mobile communication, sensors, and biomedical in recent years, the demand for accurate data information, highquality audio and image has become much more significant, which requires a high-precision Analog to Digital Converter (ADC) to process weak analog signals. As one of the core modules of ADC, the comparator’s precision, speed, stability, and noise play a key role in the performance of the whole circuit. Over the years, those performance has been improved a lot by both designing new architectures and using advanced fabrication technology. However, the conventional comparators occupy 50%-60% of the total energy consumption of EPC, even with advanced technology and lower supply voltage. In this thesis, a new type of energy-efficient comparator, called Edge-Pursuit Comparator (EPC), is proposed, which satisfies the need for low comparison energy. The design of EPC is based on a ring oscillator, when the EPC enters the evaluation mode, two signal edges with different propagation delays will chase in it until one overlaps the other, and finally generate a stable voltage level in each output node. The circuit is built and simulated in Cadence Virtuoso using cmos22fdsoi technology. The simulation results reveal that the energy consumed per comparison is dependent on the input differential voltage, and it can be as low as 7 fJ when vin = 50 mV, which is around ten times smaller compared with conventional comparators. In addition, as the power consumption is considerable when the two input voltages are very close, a promising improvement is applied to EPC, namely connecting every node with a variable capacitor, which is called Edge-Pursuit Comparator enhanced with Capacitor (EPCC). Cadence simulation results prove that EPCC can largely lower the energy consumption under a small vin while keeping input-referred noise the same. Therefore, a combination of EPC and EPCC is expected to have prospective applications in the energy-efficient area. / Med den snabba utvecklingen av mobil kommunikation, sensorer och biomedicin under de senaste åren har efterfrågan på korrekt datainformation, högkvalitativt ljud och bild blivit mycket mer betydande, vilket kräver en högprecision Analog till Digital Converter (ADC) för att bearbeta svaga analoga signaler. Som en av ADC:s kärnmoduler spelar komparatorns precision, hastighet, stabilitet och brus en nyckelroll i prestanda för hela kretsen. Under årens lopp har dessa prestanda förbättrats mycket genom att både designa nya arkitekturer och använda avancerad tillverkningsteknik. De konventionella komparatorerna upptar dock 50%-60% av den totala energiförbrukningen för EPC, även med avancerad teknik och lägre matningsspänning. I detta examensarbete föreslås en ny typ av energieffektiv komparator, kallad Edge-Pursuit Comparator (EPC), som tillgodoser behovet av låg jämförelseenergi. Designen av EPC är baserad på en ringoscillator, när EPC:n går in i utvärderingsläget kommer två signalkanter med olika utbredningsfördröjningar att jaga i den tills den ena överlappar den andra, och slutligen generera en stabil spänningsnivå i varje utgångsnod. Kretsen är byggd och simulerad i Cadence Virtuoso med hjälp av cmos22fdsoiteknik. Simuleringsresultaten visar att energiförbrukningen per jämförelse är beroende av ingångsdifferensspänningen och den kan vara så låg som 7 fJ när vin = 50 mV, vilket är cirka tio gånger mindre jämfört med konventionella komparatorer. Dessutom, eftersom strömförbrukningen är avsevärd när de två inspänningarna är mycket nära, tillämpas en lovande förbättring på EPC, nämligen att ansluta varje nod med en variabel kondensator, som kallas Edge-Pursuit Comparator förbättrad med kondensator (EPCC). Kadenssimuleringsresultat bevisar att EPCC till stor del kan sänka energiförbrukningen under en liten vin samtidigt som ingångsreferat buller hålls detsamma. Därför förväntas en kombination av EPC och EPCC ha potentiella tillämpningar inom det energieffektiva området.