abstract: ABSTRACT As the technology length shrinks down, achieving higher gain is becoming very difficult in deep sub-micron technologies. As the supply voltages drop, cascodes are very difficult to implement and cascade amplifiers are needed to achieve sufficient gain with required output swing. This sets the fundamental limit on the SNR and hence the maximum resolution that can be achieved by ADC. With the RSD algorithm and the range overlap, the sub ADC can tolerate large comparator offsets leaving the linearity and accuracy requirement for the DAC and residue gain stage. Typically, the multiplying DAC requires high gain wide bandwidth op-amp and the design of this high gain op-amp becomes challenging in the deep submicron technologies. This work presents `A 12 bit 25MSPS 1.2V pipelined ADC using split CLS technique' in IBM 130nm 8HP process using only CMOS devices for the application of Large Hadron Collider (LHC). CLS technique relaxes the gain requirement of op-amp and improves the signal-to-noise ratio without increase in power or input sampling capacitor with rail-to-rail swing. An op-amp sharing technique has been incorporated with split CLS technique which decreases the number of op-amps and hence the power further. Entire pipelined converter has been implemented as six 2.5 bit RSD stages and hence decreases the latency associated with the pipelined architecture - one of the main requirements for LHC along with the power requirement. Two different OTAs have been designed to use in the split-CLS technique. Bootstrap switches and pass gate switches are used in the circuit along with a low power dynamic kick-back compensated comparator. / Dissertation/Thesis / M.S. Electrical Engineering 2012

The aim of this dissertation was the design, implementation and performance evaluation of a Recursive Least Squares (RLS), lattice based, adaptive, multidimensional, decision feedback equaliser (DFE) for the spectrally efficient four-dimensional digital modulation technique, re¬ferred to as Quadrature-Quadrature Phase-Shift Keying, Q2pSK. Q2PSK constitutes a relatively new modulation technique, and the application of adaptive equalisation to this technique has not yet been considered in the open literature. This dissertation represents an in depth study into the Q2PSK modulation technique, as well as the optimal implementation, in simulation, of such a modem to aid the inclusion of the adap¬tive lattice DFE, for application to high speed mobile digital communication over the V /UHF channel in the presence of multi path propagation. Specific aspects of synchronization applicable to this modem platform are also addressed. An in depth study was also conducted into the realisation of a V /UHF channel simulation, capable of producing a Ricean and/or Rayleigh fad¬ing multipath propagation environment for the evaluation of the modem platform and adaptive equaliser structure. The theoretical analysis of the effect of multi path on a Q2PSK signal led to the correct design of the adaptive lattice structure, as well as the correct interfacing of the equaliser to the receiver platform. The performance of the proposed synchronisation strategies, in tandem with the equalisation technique were evaluated for several static, as well as fading multipath channels. The simulation results obtained show the equaliser operates correctly, and can give large performance gains over the static matched filter (matched to the transmitted waveform) implementation of the modem platform. Several simulations were specifically designed to highlight the performance limitations of the adaptive equalisation technique. / Dissertation (MEng (Digital Communication))--University of Pretoria, 2006. / Electrical, Electronic and Computer Engineering / unrestricted

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This paper demonstrates conversion of an analog filter into a digital filter using computer aided software. The filter design to be demonstrated is a common third order Butterworth filter. This paper is not an attempt to review all filter designs or applications, but rather the attempt is to give a detailed explanation of the steps required to design almost any digital filter. No knowledge of the Intel Series 210 microcomputer development system is assumed. The appendices contain introduction to the Series 210 system. Chapter I demonstrates the steps needed to design this filter without computer aid. Included are both analog and digital filter response characteristics. Chapter II supplemented with Appendix C demonstrates the computer aided filter design. Again, filter characteristics are included. Chapter III compares the results of Chapter I and II. Even though this paper attempts to be inclusive of most of the computer details, it should not be used in exclusion of the available Series 210 manuals.

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This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014

Analog-to-digital converter (ADC) is the main workhorse in a digital waveform recorder. Strictly speaking, an ADC is supposed to perform uniformly, irrespective of the characteristics of the signal to be acquired. However, because of certain hardware related inconsistencies, its performance declines, particularly, when acquiring non-repetitive, fast-rising, high frequency signals. The error and distortion contributed due to its declining performance, for the entire range of signals, can be comprehensively characterized by the static and dynamic nonlinearities. Actual testing of ADCs is the only way of estimating these indices. These characteristics reveal information at the microscopic level, such as bit-level aberrations, code transitions, response and settling trends, etc. These tests attain greater significance, when the digitizer is part of a reference measuring or a calibration system, because, the levels of accuracies to be achieved in such a setup may become comparable to the error introduced by the ADC. Hence, testing ADCs is a priority. International and national standards exist for testing digital waveform recorders and ADCs. For several years, the matter related to reducing static test time of high-resolution ADCs was highlighted through many publications. A critical examination of the literature indicates the major schools-of-thought pursued so far, are, (i) refinements to ramp/triangular signal based static testing, (ii) proposals for use of alternative methods and/or test signals for static test, (iii) innovative ways of achieving a relaxation in signal source requirements and, (iv) efforts to combine static and dynamic test into a single test with an appropriate test signal. As a consequence of the literature review, objectives of the thesis were formulated. They attempt to resolve- (i) Conceive a suitable test signal for simultaneous estimation of static and dynamic nonlinearity through a single test (ii) Explore possibility of employing a low-linearity ramp signal to estimate static nonlinearity (iii) Estimating static nonlinearity by exploiting linearity property of a sine signal • In the first part of the thesis, a method is proposed for the concurrent estimation of static and dynamic nonlinearity characteristics of an ADC, with the application of a single test signal. The novelty arises from the fact that the test signal proposed is new, and so is the concept of extracting the static and dynamic nonlinearity from the ADC output. This was achieved by conceiving a test signal, comprising of a high frequency sinusoid (which addresses the dynamic requirement), modulated by a low frequency ramp (which addresses the static requirement). • Static characteristics of an ADC can be determined directly from the histogram-based quasi-static approach by measuring the ADC output, when excited by an ideal ramp/triangular signal of sufficiently low frequency. This approach requires only a fraction of time compared to the conventional DC test, is straightforward, easy to implement, and, in principle is an accepted method as per the revised IEEE-1057. However, the only drawback is that ramp signal sources are not ideal. Thus, nonlinearity present in the ramp signal gets superimposed on the measured ADC characteristics, which renders them, as such, unusable. The second part of the work describes a proposal to get rid of the ramp signal nonlinearity, before it is applied to the ADC. A simple method is presented which employs a low-linearity ramp signal, but yet causes only a fraction of influence on the measured ADC static characteristics. • The third part of the thesis describes a novel method to estimate the actual static characteristics of an ADC using a low frequency sine signal, say, less than 10 Hz, by employing the histogram-based approach. It is based on the well known fact that variation of sine signal is ‘reasonably linear,’ when the angle is small. In the proposed method, the ADC under test has to be ‘fed’ with this ‘linear’ portion of the sine wave. Due to harmonics and offset in input excitation, this ‘linear’ part of the sine signal is marginally different, compared to an ideal ramp signal of equal amplitude. However, since it is a sinusoid, this difference can be accurately determined and later compensated from the measured ADC output. Thus, the corrected ADC output will correspond to the true ADC static nonlinearity. The proposed approach successfully addresses all the three concerns while estimating static linearity, i.e. it is time-efficient, excites all the ADC code-bins reasonably uniformly and tackles the source linearity issue quite nicely. These proposals are novel, simple, easy to implement, time-efficient and importantly static nonlinearity characteristics determined from them are in good agreement with that estimated by the original DC-based technique. Implementation of each method is discussed along with experimental results, for two 8-bit digital oscilloscopes and a 10-bit real time digitizer. Further details are presented in the thesis.

Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical and Computer Engineering.

by Leung Sze-wing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 79-84). / Abstracts in English and Chinese. / ACKNOWLEDGEMENT --- p.II / ABSTRACT --- p.III / 摘要 --- p.V / CONTENTS --- p.VI / Chapter CHAPTER 1 --- INTRODUCTION --- p.1 / Chapter 1.1 --- Objectives --- p.1 / Chapter 1.2 --- Prevalence of Heart Diseases --- p.1 / Chapter 1.3 --- Importance of ECG Monitoring --- p.2 / Chapter 1.4 --- Wireless Electrode --- p.2 / Chapter 1.5 --- Analogue-to-Digital Converters --- p.3 / Chapter 1.6 --- Organization of Thesis --- p.4 / Chapter CHAPTER 2 --- LITERATURE REVIEW --- p.5 / Chapter 2.1 --- Telemetry --- p.5 / Chapter 2.1.1 --- "Definitions of ""Telemetry “" --- p.5 / Chapter 2.1.2 --- Advantages of Telemetry --- p.6 / Chapter 2.1.3 --- History of Telemetry --- p.7 / Chapter 2.1.4 --- Special Considerations on Telemetry System --- p.10 / Chapter 2.2 --- Sigma-Delta Converter --- p.12 / Chapter 2.2.1 --- Conventional Digitizing Circuitry --- p.12 / Chapter 2.2.2 --- "Single, Dual-Slope A/D Converters" --- p.13 / Single-Slope A/D Converter --- p.13 / Dual-Slope Converter --- p.75 / Chapter 2.2.3 --- Successive Approximation (SAR) --- p.17 / Chapter 2.2.4 --- Flash Converters --- p.18 / Chapter 2.2.5 --- Sigma-Delta Converter --- p.18 / Chapter 2.3 --- Conclusion --- p.20 / Chapter CHAPTER 3 --- WIRELESS ELECTRODE --- p.21 / Chapter 3.1 --- """Single Electrode"" Measurement" --- p.21 / Chapter 3.2 --- VSE (Virtual Single Electrode) --- p.21 / Concentric Electrode --- p.21 / Chapter 3.3 --- WE (Wireless Electrode) --- p.24 / Chapter 3.4 --- Discussion --- p.29 / Chapter CHAPTER 4 --- SIGMA-DELTA CONVERTER FOR ECG SIGNALS --- p.30 / Chapter 4.1 --- Motivations --- p.30 / Chapter 4.2 --- Baseband Application --- p.31 / Chapter 4.2.1 --- Simulation Results --- p.31 / Chapter 4.2.2 --- Experimental Results --- p.48 / Chapter 4.3 --- Wireless Application --- p.58 / Chapter 4.3.1 --- General Description --- p.58 / Chapter 4.3.2 --- Simulation Results --- p.59 / Chapter 4.3.3 --- Scenario 1 (Analogue Decoding) --- p.70 / Chapter 4.3.4 --- Scenario II (Digital Decoding) --- p.73 / Chapter 4.4 --- Discussion and Conclusion --- p.76 / Chapter CHAPTER 5 --- CONCLUSION AND FUTURE WORK --- p.77 / Chapter 5.1 --- General Conclus ion --- p.77 / Chapter 5.2 --- Future Work --- p.78 / BIBLIOGRAPHY --- p.79 / LIST OF ABBREVIATIONS --- p.85