Thesis (M.A. (Communication studies)) -- University of Limpopo, 2019 / The rates of Internet uses are still devastatingly low especially in developing countries and South Africa is no exception. However, South Africa has had a state policy commitment to attain Internet access for those who have been unconnected in the post Apartheid era (Electronic Communication Act, No 36 of 2005). The problem is that the policy application has been one-sided, only focusing on providing public fixed Internet access through community libraries, Thusong service centres, hospitals and public schools. While this effort is credible, it does little to address the upsurge of mobile Internet access that is increasingly characterising the digital age. The age of digital mobility represents a shift from fixed public Internet access to individualised mobile Internet access through mobile phones. However, the high prices of mobile Internet data make Internet access exclusionary in South Africa, making the needy persons to remain outside of the digital revolution. This study explored issues regarding the high cost of Internet data in South Africa and suggests ways on how universal service and access policy can be formulated to focus on individualised mobile Internet connection. Using a mixed method approach, a convenience sampling technique was used to recruit 200 University of Limpopo students to participate in a survey, and a purposive sampling technique was used for selecting one official from the Independent Communication Authority of South Africa (ICASA) and another official from the Universal Service and Access Agency of South Africa (USAASA) to participate in the standardised semi structured interview. The results indicate that unless the universal service and access policy focuses on addressing the individualised mobile Internet access for needy persons, tapping the benefits that the Internet provides will remain out of reach for many South African youths.

Dans l’âge des objets connectés, circuits conventionnels implémenté sur silicium ne sont pas la seule option pour réaliser des interfaces des capteurs. Dispositifs électroniques implémentés sur substrats souples sont aussi une option intéressante comme interface des capteurs dans notre quotidien, e.g: dans des vêtements, emballages, peau et dedans notre corps humain. Dans cette thèse nous proposons une formalisation de :-La procédure de fabrication de transistors en utilisant des matériaux organiques et flexibles. -La conception de circuits analogiques et numériques en utilisant ces transistors. Les contributions de cette thèse sont :• Optimisation de la procédure de fabrication et caractérisation de 2 technologies : la première fabriqué en utilisant des masques (« shadow masks » en anglais) avec un procès relativement « simple à implémenter ». La deuxième par un procès en utilisant la photolithographie et l’auto alignement. • Modélisation et extraction de paramètres pour prévoir leurs variations dans la conception de circuits.• Customisation des outils CAO « Open Source » VLSI (Alliance ©) pour la conception des circuits et layouts des transistors organiques.• Conception, fabrication et mesure des circuits analogiques (OTAs, comparateurs et convertisseurs analogiques-numériques) et circuits numériques simples (inverseurs, portes logiques, bascules). Ce travail a eu des résultats intéressants et il ouvre un ample spectre d’applications dans l’avenir dans le domaine de l’électronique flexible et organique. / In the era of “Internet of Things”, conventional silicon-based circuits are not the only option to realize sensor interfaces. Electronic devices based on flexible materials are an interesting approach to interface with sensors connected to our everyday life, e.g.: clothes, packages, skin and into the human body. In this thesis, we propose a formalization of the:- Transistor fabrication process using organic and flexible materials.- Analog and digital circuit design using these transistors. The main contribution of this work can be summarized in the following:- Optimization of the fabrication and characterization process of two technologies: the first by shadow masks with an easy-to-fabricate procedure, the second by self-alignment and photolithography.- Modeling and parameter extraction for process variation aware analog design.- Customization of an open source VLSI CAD tools (Alliance©) for circuit design and layout of OTFT.- Design, fabrication and measurement of OTFT analog front-ends (OTAs, Comparators, Analog-to-Digital Converters,…) and basic digital circuits (Inverters, Logic Gates, …).This work achieved very interesting results and it opens a wide scope of future applications in the field of Flexible organic electronics.

Thesis (PhD)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a better instrument. The largest radio telescope in the world will consist of several arrays, the largest of which, consisting of more than 3000 dishes, will be situated primarily in South Africa. The ambitions of the SKA are grand and their realisation requires technology that does not exist today. Current plans see signals in the band of interest ampli ed, channelised, mixed down and then digitised. An all-digital frontend could simplify receiver structure and improve its performance. Semiconductor (analog-to-digital converters) ADCs continue to make great progress and will likely nd applications in the SKA, but superconductor ADCs bene t from higher clock speeds and quantum accurate quantisation. We propose a superconducting softwarede ned radio frontend. The key component of such a frontend is a superconducting ash ADC. We show that employing such an ADC, even a small- to moderately-sized one, will signi cantly improve the instantaneous bandwidth observable by the SKA, yet retain adequate signal-to-noise ratio so as to achieve a net improvement in sensitivity. This improvement could approach factor 2 when compared to conventional technologies (at least for continuum observations). We analyse key components of such an ADC analytically, numerically and experimentally and conclude that fabrication of such an ADC for SKA purposes is certainly possible and useful. Simultaneously, we address the power requirements of high-performance computing (HPC). HPC on a hitherto unprecedented scale is a necessity for processing the vast raw data output of the SKA. Utilising the ultra-low-energy switching events of superconducting switches (certain Josephson junctions), we develop rst demonstrators of the promising eSFQ logic family, achieving experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the applicability of the eSFQ design concept to arbitrary (unclocked) gates. / AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat nog nie vandag bestaan nie. Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer, afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier sagteware-gede nieerde radio kopstuk voor. Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \ ash" ADO. Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte, die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities, numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir SKA doeleindes beide moontlik en nuttig is. Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid vir die verwerking van die enorme rou data uitset van die SKA. Deur die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep na arbitr^ere (ongeklokte) hekke uit te brei.

Afin de réaliser un appareil innovant pour la mesure de gaz polluants, la société SVS@CAP s’est associée avec le laboratoire de physique corpusculaire en 2009 pour la création du projet EREBUS. Ce projet a pour but la réalisation d’un ensemble de dispositifs sans fil permettant d’effectuer une surveillance de la concentration de gaz polluants. L’autonomie et la compacité d’un tel dispositif étant essentielles, la problématique principale porte sur la réduction de la consommation. A partir d’une première étude menée sur les différentes technologies existantes, les capteurs électrochimiques ont été identifiés comme les moins consommateurs d’énergie. Pour chacun des gaz cibles, un modèle électrique du capteur associé a été déterminé. A partir de ces modèles, une architecture dédiée et épurée a pu être déduite. Pour atteindre et même dépasser les objectifs de consommation, les efforts ont aussi été portés sur un dimensionnement avec la méthode gm/id. La réalisation de cette électronique intégrée a permis d’atteindre une consommation de l’ordre du μW pour chaque voie de mesure. Enfin, pour compléter la chaîne de lecture, plusieurs architectures de convertisseurs ont été étudiées et réalisées pour fonctionner à des fréquences déchantillonnage proches du Hz. Les consommations obtenues pour les convertisseurs sont limitées avec comme ordre de grandeur la centaine de nW. / In order to realize an innovative product for pollutants in the atmosphere, SVS@CAP company started in 2009 the EUREBUS project in collaboration with the "Laboratoire de Physique Corpusculaire". The aim of this project is to design a wireless equipement to measure gas concentrations. The key issues of this project are concerning the autonomy as well as the small size of the product. In consequence an integrated and low power electronics remains essential. From a first study of the existing technologies to detect gaz concentrations, electrochemical sensors were selected because of their low power consumption. For each of the target gas, an electrical model was determined. From those models, a specific architecture was designed. A special effort was made on the energy consumption thanks to the use of the gm/id methodology which was necessary to achieve and exceed the specifications. The final order of the power consumption of the front-end developped and realized is around the μW. Finally, in order to complete the chain of acquisition, some architectures of analog to digital converter were studied, developped and realized with sample frequencies close to the Hz. The power consumptions of the converters developped are limited to the order of the hundreds of nW.

Multiple-input multiple-output (MIMO) radars, which utilize multiple transmitters and receivers to send and receive independent waveforms, have been actively investigated as a next generation radar technology inspired by MIMO techniques in communication theory. Complementary metal-oxide-semiconductor (CMOS) technology offers an opportunity for dramatic cost and size reduction for a MIMO array. However, the resulting formidable signal processing burden has not been addressed properly and remains a challenge. On the other hand, from a block-level point of view, an analog-to-digital converter (ADC) is required for mixed-signal processing to convert analog signals to digital signals, but an ADC occupies a significant portion of a system's budget. Therefore, improvement of an ADC will greatly enhance various trade-offs. This research presents an alternative and viable approach for a MIMO array from a system architecture point of view, and also develops circuit level improvement techniques for an ADC. This dissertation presents a fully-integrated analog pulse compressor (APC) based on an analog matched filter in a mixed signal domain as a key block for the waveform diversity MIMO radar. The performance gain of the proposed system is mathematically presented, and the proposed system is successfully implemented and demonstrated from the block level to the system level using various waveforms. Various figures of merit are proposed to aid system evaluations. This dissertation also presents a low-power ADC based on an asynchronous sample-and-hold multiplying SAR (ASHMSAR) with an enhanced input range dynamic comparator as a key element of a future system. Overall, with the new ADC, a high level of system performance without severe penalty on power consumption is expected. The research in this dissertation provides low-cost and low-power MIMO solutions for a future system by addressing both system issues and circuit issues comprehensively.

Thesis (Master').

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.

Este trabalho apresenta a modelagem e implementação em FPGA de sistemas digitais de compensação de desvios para TIADC. O desenvolvimento de todo este trabalho seguiu uma metodologia top-down. Seguindo esta metodologia foi elaborada a modelagem comportamental de um TIADC de dois canais e seus respectivos desvios de offset, ganho e clock skew em Simulink. Além da modelagem comportamental de sistemas digitais para a compensação destes desvios. Para o desvio de clock skew foi utilizada a compensação através de filtros de delay fracionário, mais especificamente, a eficiente estrutura de Farrow. A definição de qual método seria utilizado para o projeto do filtro, e da estrutura de Farrow, exigiu um estudo de diversos métodos de projeto apresentados na literatura. Os sistemas digitais de compensação modelados foram convertidos em código VHDL, para implementação e validação em FPGA. A validação destes sistemas foi realizada utilizando a metodologia de teste FPGA In Loop. Os resultados obtidos com os compensadores de desvio do TIADC demonstram o elevado ganho de desempenho fornecido por estas estruturas. Além deste resultado, este trabalho ilustra o potencial das metodologias de desenvolvimento, implementação e teste em FPGA utilizadas para a obtenção destes compensadores. / This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Este trabalho apresenta a modelagem e implementação em FPGA de sistemas digitais de compensação de desvios para TIADC. O desenvolvimento de todo este trabalho seguiu uma metodologia top-down. Seguindo esta metodologia foi elaborada a modelagem comportamental de um TIADC de dois canais e seus respectivos desvios de offset, ganho e clock skew em Simulink. Além da modelagem comportamental de sistemas digitais para a compensação destes desvios. Para o desvio de clock skew foi utilizada a compensação através de filtros de delay fracionário, mais especificamente, a eficiente estrutura de Farrow. A definição de qual método seria utilizado para o projeto do filtro, e da estrutura de Farrow, exigiu um estudo de diversos métodos de projeto apresentados na literatura. Os sistemas digitais de compensação modelados foram convertidos em código VHDL, para implementação e validação em FPGA. A validação destes sistemas foi realizada utilizando a metodologia de teste FPGA In Loop. Os resultados obtidos com os compensadores de desvio do TIADC demonstram o elevado ganho de desempenho fornecido por estas estruturas. Além deste resultado, este trabalho ilustra o potencial das metodologias de desenvolvimento, implementação e teste em FPGA utilizadas para a obtenção destes compensadores. / This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Este trabalho aborda os soft errors em conversores de dados analógico-digitais e a mitigação usando redundância e diversidade. Nas tecnologias CMOS recentes, os efeitos singulares (SEEs, Single Event Effects) são um grupo de efeitos da radiação espacial que afetam a confiabilidade e disponibilidade dos sistemas. Os soft errors são SEEs que não danificam diretamente o sistema e podem ser posteriormente corrigidos. Seus principais subgrupos são o Single Event Upset (SEU), o Single Event Transient (SET) e o Single Event Functional Interrupt (SEFI). Uma das técnicas em nível de sistema amplamente usadas para proteger os circuitos eletrônicos desses efeitos é a Redundância Modular Tripla (TMR, Triple Modular Redundancy), que pode ainda ser melhorada com a adição da técnica de diversidade. Nesse contexto, esse trabalho adota um esquema baseado nessas duas técnicas para a implementação de um sistema de aquisição de dados (SAD) analógico-digital. Seus objetivos são observar o comportamento dos conversores de dados frente aos soft errors e avaliar a eficácia de um sistema baseado em TMR e diversidade espacial-temporal contra esses efeitos da radiação. A implementação desse SAD em um SoC (System-on-Chip) da Cypress Semiconductor, chamado PSoC 5LP e fabricado em tecnologia CMOS de 130 nm, propiciou a realização de dois estudos: no primeiro, é realizada a irradiação com nêutrons, caso de particular interesse para os equipamentos eletrônicos embarcados em aviões; e no segundo, são realizadas injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM do PSoC 5LP. O resultado da irradiação do primeiro estudo foi a não observância de erros, o que impediu cumprir os objetivos propostos para esse teste. Essa situação permitiu duas observações principais: primeiro, o fluxo de nêutrons do experimento é uma característica fundamental que impacta na capacidade de se observar os efeitos da radiação, principalmente quando a seção de choque do circuito em análise é baixa; e segundo, de que a probabilidade de ocorrerem mascaramentos de SETs nos circuitos combinacionais e analógicos é elevada, o que contribui significativamente para reduzir a sensibilidade desses circuitos. Para avaliar a eficácia do sistema baseado em TMR e diversidade espacial-temporal foi então realizada uma investigação teórica baseada em análise combinatória, e os resultados mostraram que a adição de diversidade temporal gera, em comparação ao TMR clássico, um ganho significativo na tolerância de falhas duplas e múltiplas, ao preço de um aumento do atraso do circuito. Os resultados das injeções de falhas por software e em tempo de execução nos registradores de controle dos periféricos e na SRAM mostraram que apenas um baixo percentual das falhas injetadas é detectado na forma de erros, convergindo para a justificativa de que os mascaramentos foram determinantes para a não observância de erros no primeiro estudo, de injeção de falhas por radiação. Também verificou-se que os registradores de controle dos periféricos são mais importantes no nível de aplicação do que os dados da memória SRAM. Considerações sobre a auto injeção de falhas e auto monitoramento sugerem que a utilização desses conceitos pode trazer diversas limitações e complicadores aos testes. / The present thesis addresses the soft errors in analog-to-digital data converters and mitigation of such errors using redundancy and diversity. In modern CMOS technologies, the Single Event Effects (SEEs) comprises an important group of space radiation effects that influence the reliability and availability of the systems. Soft errors are SEEs that do not directly damage the system and that can be further corrected. Their main subgroups are the Single Event Upset (SEU), the Single Event Transient (SET) and the Single Event Functional Interrupt (SEFI). One of the system level techniques broadly used to protect the electronic circuits against these effects is the Triple Modular Redundancy (TMR), which may be improved with the addition of the diversity technique. In this context, this work proposes a scheme based on these two techniques to implement a tolerant analog-to-digital data acquisition system (DAS). The main objectives are to observe the behavior of the data converters under soft errors, and evaluate the effectiveness of a system based on TMR and spatial-temporal diversity on mitigating these radiation effects. The implementation of this DAS in a Programmable SoC (System-on-Chip) from Cypress Semiconductor (PSoC 5LP) manufactured in 130 nm CMOS, allowed the development of two studies. In the first one, an irradiation with neutrons is performed, case of particular interest to electronic equipment embedded on planes. In the second study, runtime software fault injections are performed at the peripheral control registers and SRAM of the studied device. As a result from irradiation on the first study no errors were found, what does not allowed meet the objectives of this test. This situation allow two main observations: first, the neutron flux of the experiment is a key feature that influences the ability to observe the radiation effects, mainly when the cross section of the circuit in analysis is low; and second, the probability of occurring SETs masking in combinational and analog circuits is high, which contributes significantly to reduce the sensibility of these circuits. To evaluate the effectiveness of a system based on TMR and spatial-temporal diversity then was performed a theoretical investigation based on combinatorial analysis, and the results show that the addition of temporal diversity generates a significant gain in tolerating double and multiple faults, if compared to the classical TMR, at the price of an increase in the circuit delay. The results of the second study, performed by runtime software fault injections at the peripheral control registers and SRAM, showed that only a low percentage of injected faults is detected as errors, according to the justification that no errors were found on irradiation of neutrons due to masking. Also was verified that at the application level the peripheral control registers are more important than the data stored in the SRAM memory. Considerations for faults self-injection and self-monitoring were done, suggesting that the use of these concepts may bring numerous limitations to the test.