Abstract The rapid growth in the wireless communications markets together with the emerging need for high-bit-rate (≫ 100 Mb/s) multimedia/data services are pushing the usage of radio spectrum resources below 10 GHz to the uttermost limit. The lack of bandwidth has led to an extensive development of mobile/fixed BWA systems for the higher microwave and millimetre-wave regions up to the V-band frequencies (50–75 GHz). In order for these systems to have mass deployment and to meet cost-sensitive consumer markets’ requirements, their cost and size must be reduced from current levels. One of the most viable packaging approaches to satisfy these demands is the low-temperature co-fired ceramic (LTCC) based system-in-package (SiP) module technology combined with fully automated surface-mount assembly techniques. However, one of the main challenges of this approach has been previously associated with the broadband radio frequency (RF) and reliability performance constraints of the board-level solder joints in LTCC/PCB assemblies. In this thesis the primary focus is to tackle these limitations and significantly extend the feasibility of the LTCC module technology to various wireless/mixed-signal packaging applications. The thesis is divided into three main parts. In the first part, design, modelling and implementation of vertical package transitions (BGA, flip-chip, substrate via) over a very wide frequency range are presented. In the second part, the emphasis is on the improvement of the thermal fatigue endurance of the board-level solder joints in the LTCC/PCB assemblies. In the last part, the results are merged to realize a high-performance LTCC module platform for use in a wide variety of SiP products in the telecommunication sector. The flip-chip, substrate-via and BGA transition structures exhibited excellent signal transmission properties up to the V-band frequencies. The developed equivalent circuit models of the transitions matched well with the measurements. Cascading the transitions together allows the building of different combinations of vertical interconnection paths in SiP modules. To demonstrate this, a surface-mountable LTCC filter package for K-band radio link frequencies was implemented. The developed composite BGA solder joint structure with plastic-core solder balls significantly enhanced the thermal fatigue life in LTCC/PCB assemblies in different thermal cycling conditions, indicating adequate board-level reliability for many practical LTCC-BGA packaging applications. Moreover, electromagnetic analysis showed that the use of the plastic-core solder ball has no detrimental impact on the RF performance of the solder joint. Finally, based on the obtained results a reliable lead-free LTCC-BGA module platform was developed for broadband packaging applications. The BGA module platform with a size of 15 mm × 15 mm included 38 low-frequency and two wideband RF input/output connections up to the K-band frequencies. The module structure also allowed plenty of space to mount discrete SMD/bare-die components on the surface and/or to embed passive components in the 1.2 mm thick substrate. Preliminary thermal cycling results of the soldered LTCC/PCB assemblies demonstrated sufficient reliability for telecommunication applications. Therefore, the presented module platform can serve as a physical building block for various wireless/mixed-signal SiP products, and hence significantly reduce their development time and associated costs.

The traditional design of printed circuit board assembly focuses on finding a set of parameter values (that characterizes the process), such that the desired circuit performance specifications are met. It is usually assumed that this set of values can be accurately realized when the circuit or the assembly is built. Unfortunately, this assumption is not realistic for assemblies produced in mass scale. Fluctuations in manufacturing processes cause defects in actual values of the parameters. This variability in design parameters, in turn, causes defects in the functionality of the assemblies. The ratio of the acceptable assemblies to total assemblies produced constitutes the yield of the assembly process. Assembly yields of area array packages are heavily dependent on design of the board as much as package and process parameters. The economics of IC technology is such that the maximization of yield rather than the optimization of performance has become the topic of prime importance. The projected value of yield has always been a factor for consideration in the advancement of Integrated Chip technology. Due to considerable reduction in the package size, minimum allowable tolerance and tight parameter variations, electronic assemblies have to be simulated, characterized and tested before translating them to a production facility. Also, since the defect levels are measured in parts per million, it is impractical to build millions of assemblies for the purpose of identifying the best parameter. A mathematical model that relates design parameters and their variability to assembly yield can help in the effective estimation of the yield. This research work led to the development of a mathematical model that can incorporate variability in the package, board and assembly related parameters and construction of an effective methodology to predict the assembly yield of area array packages. The assembly yield predictions of the model are based on the characteristics of input variables (whether they follow a normal, empirical or experimental distribution). By incorporating the tail portion of the parameter distribution (up to ±6 standard deviation on normal distribution), a higher level of accuracy in assembly yield prediction is achieved. An estimation of the interaction of parameters is obtained in terms of the expected number of defective joints and/or components and a degree of variability around this expected value. As an implementation of the mathematical model, a computer program is developed. The software is user friendly and prompts the user for information on the input variables, it predicts the yield as expected number of defective joints per million and expected number of defective components (assemblies) per million. The software can also be used to predict the number of defects for a user-specified number of components (less or more than one million assemblies). The area array assembly yield model can be used to determine the impact of process parameter variations on assembly yields. The model can also be used to assess the manufacturability of a new design, represent the capability of an assembly line for bench marking purposes, help modify designs for better yield, and to define the minimum acceptable manufacturability standards and tolerances for components, boards and designs. / Master of Science

This research developed a novel, non-wire bond semiconductor interconnect technology, termed the Dimple Array interconnect (DAI), with significantly improved electrical, thermal and mechanical characteristics for power electronics applications. In the DAI structure, electrical connections onto the devices are achieved by solder bumps formed between the silicon device and arrays of dimples stamped on a metal sheet flex. This research first presents the design of the materials, electrical and thermal performance, reliability, and the fabrication process of the DAI. It was found that due to the use of solder material, the current handling capability and thermal management of Dimple Array interconnected devices are significantly better than those using wire bonds. In addition, the shorter and wider solder joints reduce parasitics, which is a serious problem in wire bond interconnects. The proposed fabrication process of the DAI is simpler than other developing integrated power packaging technologies, such as flip chip and deposited metallization integration. DAI was successfully demonstrated in a half-bridge power electronics module with much improved electrical characteristics. The study then focuses on the thermomechanical reliability of Dimple Array packages as compared to conventional controlled collapse bonding (CCB) flip chip packages. Experimental approaches, such as power cycling and temperature cycling tests, and numerical simulation with the help of finite element analysis (FEA) were used. The thermal cycling test shows that dimple solder joints display an eightfold reliability improvement over the conventional CCB solder joints. The power cycling test showed that the measured forward voltage can not reliably reflect the integrity of the solder joint interconnect. However, from metallographic cross-section images of these samples, it was concluded that the DAI solder joints are more reliable than the CCB solder joints under power cycling conditions. FEA results showed excellent correlation with experiments in predicting that the Dimple Array solder joints are more fatigue-resistant due to a reduced stress/strain concentration. Furthermore, failure mechanisms were explored using the mapped stress/strain distribution within the models. It was found that the CCB solder joint has a highly localized strain concentration at the device/solder interface, while strains are more uniformly distributed over the whole Dimple Array solder joint. / Ph. D.

The interfacial reactions of Sn-Zn and Sn-Zn-Al solder balls with Au/Ni surface finish under aging at 150¢J were investigated. With microstructure evolution, quantitative analysis, elemental distribution by X-ray color mapping from an electron probe microanalyzer (EPMA), the reaction procedure of phase transformation was proposed. During the reflow, Au dissolved into the solder balls and reacted with Zn to form £^-Au3Zn7. As aging time increased, £^-Au3Zn7 transformed to £^3-AuZn4. Finally, Zn precipitated near the Au-Zn intermetallic compound. On the other hand, Zn reacted with the Ni layer and formed Ni5Zn21. But the Al-Au-Zn IMC formed at the interface of Sn-Zn-Al solder balls, the reaction of Ni with Zn was inhibited. Even though the aging time increased to 50 days, no Ni5Zn21 was observed. The Joule effect was more apparent than the electromigration in the biased solder balls. First of all, the new phase (Au, Ni)Zn4 was proposed in the biased condition and in 175¢Jaging. Secondly, the thickness of the Ni5Zn21 IMC were the same between the anode and the cathode. Finally, We directly measure the temperature of the biased solder balls which was up to 173¢J.

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Abstract In the interest of improving reliability, electrical monitoring methods were utilized to observe the degradation of electronics interconnections while simultaneously characterizing accelerated testing-induced changes in test structures by means of optical examination, X-ray, scanning acoustic microscopy and scanning electron microscopy. To improve the accuracy of lifetime prediction for the PCSB interconnections investigated in this work, a modified Engelmaier’s solder joint lifetime prediction model was recalibrated. The results show that with most of the presented lead-free (SAC387, SAC405, SAC-In) solder and structure combinations with a large global thermal mismatch (ΔCTE > 10 ppm/°C), lifetime was adequate in the presented TCT ranges of 0‒100 °C and −40‒125 °C, while the amount of non-preferred crack types, i.e. ceramic cracks, was minimized. Degradation of interconnections was characterized using RF measurements both during TCT and intermittently during TCT breaks. A grounded coplanar waveguide was arranged either in a straight back-to-back configuration or together with a filter module with a passband at 22‒24 GHz—both with two transitions—and characterized during cycling breaks up to 25 GHz and 30 GHz, respectively. Besides off-cycle measurements, in-cycle measurements were done on an antenna structure with an in-band at 10‒11 GHz, up to 14 GHz. The results show that the signal response was initially affected at some frequencies as short-duration (< 1 s) glitches in the monitored signal when measured during cycling in 0‒100 °C TCT. Later on the degradation could be observed in the whole frequency band as TCT was continued. Development of the semi-empirical lifetime prediction model for PCSB interconnections showed the temperature range dependency of the correction term to be a second order polynomial instead of a logarithmic one. For components with PCSB BGA, promising prediction results were achieved which differed from the realized lifetime by less than 0.5% at best. / Tiivistelmä Elektroniikkaliitosten rikkoontumisen seurantaan tarkoitettuja sähköisiä monitorointimenetelmiä kehitettiin samanaikaisesti karakterisoimalla testauksella liitoksiin aikaansaatuja muutoksia optisesti, akustisella mikroskoopilla sekä röntgen- ja pyyhkäisyelektronimikroskoopeilla. Liitosten eliniän ennustamiseen soveltuva muokattu Engelmaierin malli kalibroitiin PCSB-liitosten elinikäennusteen tarkkuuden parantamiseksi. Tulosten perusteella useimmille tässä työssä käytetyille lyijyttömille (SAC387, SAC405, SAC-In) juotteille ja suuren termisen epäsovituksen (ΔCTE > 10 ppm/°C) rakenneyhdistelmille eliniät lämpösyklaustesteissä 0‒100 °C ja −40‒125 °C alueilla olivat riittävät ja haitallisimpien murtumien, eli keraamimurtumien, määrä saatiin minimoiduksi. RF-mittauksia käytettiin liitosten vikaantumisen seurantaan sekä lämpösyklauksen aikana että syklausten välillä. Maadoitettua koplanaarista aaltojohtoa käytettiin joko suoraan perättäiskytkennässä tai suodatinmoduulin kanssa, jonka päästökaista oli 22–24 GHz. Rakenteet karakterisoitiin syklausten välillä 25 GHz ja 30 GHz asti tässä järjestyksessä. Näiden mittausten lisäksi 10–11 GHz kaistalla toimivaa antennirakennetta karakterisoitiin syklauksen aikana 14 GHz asti. Tulokset osoittavat, että signaalivasteen muutos ilmenee aluksi joillakin taajuuksilla lyhyinä, alle 1 s mittaisina häiriöpiikkeinä, 0‒100 °C syklauksen aikana. Syklauksen edetessä vasteen huononeminen havaitaan myöhemmin koko mittausalueella. Puolikokeellista elinikäennustemallia tarkasteltaessa havaittiin, että PCSB-liitosten lämpötila-alueesta riippuvia korjauskertoimia kuvasivat logaritmisen riippuvuuden sijaan parhaiten toisen asteen polynomifunktiot. PCSB BGA ‒rakenteille saadun ennusteen ja toteutuneen eliniän välinen ero oli pienimmillään alle 0.5 %.

This thesis deals with possibilities of increasing the yield of BGA repair process. First there is mentioned basic problematics and its notions, problems and possibilities. Next it deals with technological aspects of repairing of devices in BGA covers. Also there is mentioned basic problematics of evaluating of yield. There is stated current state of solving the problem and also there is suggested new design of application which would be more optimal for evaluation of the yield of process. This thesis contains results of practical testing of methods of application of flux affecting final quality of solder joints as well as kind of flux which was used. At the end

As technology progresses towards smaller electronic packages, thermo-mechanical considerations pose a challenge to package designers. One area of difficulty is the ability to predict the fatigue life of the solder connections. To do this one must be able to accurately model the thermo-mechanical performance of the electronic package. As the solder ball size decreases, it becomes difficult to determine the performance of the package with traditional methods such as the use of strain gages. This is due to the fact that strain gages become limited in size and resolution and lack the ability to measure discreet strain fields as the solder ball size decreases. A solution to the limitations exhibited in strain gages is the use of Moiré interferometry. Moiré interferometry utilizes optical interferometry to measure small, in-plane relative displacements and strains with high sensitivity. Moiré interferometry is a full field technique over the application area, whereas a strain gage gives an average strain for the area encompassed by the gage. This ability to measure full field strains is useful in the analysis of electronic package interconnections; especially when used to measure strains in the solder ball corners, where failure is known to originate. While the improved resolution of the data yielded by the method of Moiré interferometry results in the ability to develop more accurate models, that is not to say the process is simple and without difficulties of it's own. Moiré interferometry is inherently susceptible to error due to experimental and environmental effects; therefore, it is vital to generate a reliable experimental procedure that provides repeatable results. This was achieved in this study by emulating and modifying established procedures to meet our specific application. The developed procedure includes the preparation of the specimen, the replication and transfer of the grids, the use of the PEMI, interpretation of results, and validation of data by finite element analysis using ANSYS software. The data obtained maintained uniformity to the extent required by the scope of this study, and potential sources of error have been identified and should be the subject of further research.

Cette thèse, qui s’intègre dans le cadre du projet européen EMCOMIT, a pour objectif de contribuer à l’étude des circuits imprimés haute densité d’intégration comportant un nombre de couches important et des composants enterrés. La qualification de cette technologie est effectuée en conduisant des simulations et des mesures électriques sur des véhicules de tests spécifiques. L’analyse des résultats électriques permet d’évaluer l’aptitude de ces matériaux à répondre aux exigences des applications de télécommunication et de technologie de l’information rapide. La fiabilité d’un assemblage de BGA de grande taille sur un circuit imprimé a été évaluée. Des simulations thermomécaniques ont été effectuées afin de calculer les contraintes résiduelles accumulées pendant le procédé d’assemblage puis l’énergie dépensée dans les parties critiques des joints au cours d’un cycle thermique. Simultanément, des BGA reportés sur des circuits imprimés ont été placés dans une chambre climatique et ont subi des variations de températures. / This thesis, which is part of the European EMCOMIT project, aims at contributing to the study of high density printed circuit board including a great number of internal layers and embedded components. The qualification of this technology is done by the way of simulations and electrical measurements on specific test vehicles. The electrical results allow estimating the performance of materials for telecommunication applications and speed data transfer. The reliability of the assembly of the large BGA on a printed circuit board has been evaluated. Thermomechanical simulations have been done in order to compute residual stresses stored during the assembly process and the deformation energy density in the solder joints during one thermal cycle. Simultaneously BGA soldered on printed circuits have been positioned in climatic chamber and have been subjected to temperature variations.

The work deals with research and development of a new method for ball-attach process, resp. reballing process of solder bumps on package with solder ball terminals (BGA, CSP, SOP, etc.), based on research and optimization of the parameters of the final terminals. The output is specially modified templates designed for placement of solder balls before reflow soldering. Three materially different templates were investigated in the work, in addition to the commonly used stainless steel, two other newly designed templates, which used ceramic materials (96% Al2O3a AlN) with thick-layer resistance heating. Proven advantages of the method using templates directly heated by electric current are the reduction of the thermal load of BGA packages in the first soldering process, as well as the creation of a better connection between the metallization of the case and the solder ball after final soldering to the printed circuit board. During the research, development and optimization of the method, tests of the created solder bumps were performed from the point of view of mechanical strength and internal structure. In the next part of the work, a research of solder bumps soldered using infrared heaters was performed in order to determine the influence of the heat flow direction in the process of reflow soldering. The heaters were successively placed in three positions, i.e. heating from the bottom of the housing, heating from the top and both heaters simultaneously. After sample preparation, metallographic cuttings and etching, the analysis of the internal structure of the entire solder ball and the intermetallic layer at the interface of the solder and the solder pad was performed. The work represents not only a new method of soldering solder bumps, but also new knowledge to create their internal structure, which contributes to meeting the increasingly demanding requirements to achieve the required reliability and quality.