Recent trends to miniaturized systems such as smartphones and wearables, as well as the rise of autonomous vehicles relying on all-electric and smart in-car systems, have brought unprecedented needs for superior performance, functionality, and cost requirements. Transistor scaling alone cannot meet these metrics unless the remaining system components such as substrates and interconnections are scaled down to bridge the gap between transistor and system scaling. In this regard, 3D glass system packages have emerged as a promising alternative due to their ultra-short system interconnection lengths, higher component densities and system reliability enabled by the tailorable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability of glass. The research objectives are to demonstrate board-level reliability of large, thin, glass packages directly mounted on PCB with conventional BGAs at pitches of 400µm SMT and smaller. Two key innovations are introduced to accomplish the objectives: a.) Reworkable circumferential polymer collars providing strain-relief at critical high stress concentration areas in the solder joints, b.) novel Mn-doped SACMTM solder to provide superior drop test performance without degrading thermomechanical reliability. Modeling, package and board design, fabrication and reliability characterization were carried out to demonstrate reliable board-level interconnections of large, ultra-thin glass packages. Finite-element modeling (FEM) was used to investigate the effectiveness of circumferential polymer collars as a strain-relief solution on fatigue performance. Experimental results with polymer collars indicated a 2X improvement in drop performance and 30% improvement in fatigue life. Failure analysis was performed using characterization techniques such as confocal surface acoustic microscopy (C-SAM), optical microscopy, X-ray imaging, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS). Model-to-experiment correlation was performed to validate the effectiveness of polymer collars as a strain-relief mechanism. Enhancement in board-level reliability performance with advances in solder materials based on Mn-doped SACMTM is demonstrated in the last part of the thesis.The studies, thus, demonstrate material, design and process innovations for package-to-board interconnection reliability with ultra-thin, large glass packages.

Surface mount devices (SMDs), such as flip chip packages and ball grid array (BGA) packages are gaining in popularity in microelectronics industry because they provide high density inputs/outputs, better electrical and thermal performance. However, these solder bump interconnections in SMDs are sandwiched between the silicon die and the substrate, which makes them challenging to be inspected. Current non-destructive solder bump inspection techniques like electrical testing, X-ray and acoustic microscopy have some application gaps. New solder bump inspection technique is urgently needed to fill these gaps. Previous work has shown the potential of using a non-contact, non-destructive laser ultrasonics and laser interferometer based inspection system for assessing solder bump qualities. The system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages and a laser interferometer to measure the transient out-of-plane displacement on the package surface. The quality of the solder bumps can be evaluated by analyzing the out-of-plane displacement. However, there are still some gaps that need to be addressed before the system is ready on the shelf. This dissertation focuses on addressing some of these existing issues. The research work consists of the following: 1) a control interface was developed to integrate all the different modules to achieve automation. 2) a new signal-processing method for analyzing the transient out-of-plane displacement signals without requiring a known-good reference chip was developed. 3) the application scope of the system was expanded to inspect the second level solder bumps in BGA packages. Two types of process-induced defects including poor-wetting and solder bump voids were investigated. Meanwhile, solder bump fatigue caused by cyclic mechanical bending and thermal cycle was also studied using this system. 4) a finite element analysis was performed to study the thermo-mechanical reliability of solder bumps in PBGA package under cyclic thermal loads. The successful completion of the research objectives has led to a laser ultrasound solder bump inspection system prototype with more user-friendliness, higher throughputs, better repeatability and more flexibility, which accelerate the commercialization the system.

Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2016-12-23T12:17:06Z No. of bitstreams: 1 Tiago de Freitas Machado_.pdf: 13489744 bytes, checksum: 639cbc0fc0de3f47a3c757ff594540e0 (MD5) / Made available in DSpace on 2016-12-23T12:17:06Z (GMT). No. of bitstreams: 1 Tiago de Freitas Machado_.pdf: 13489744 bytes, checksum: 639cbc0fc0de3f47a3c757ff594540e0 (MD5) Previous issue date: 2016-09-15 / itt Chip - Instituto Tecnológico de Semicondutores da Unisinos / O processo de soldagem de esferas em componentes do tipo esferas organizadas em matriz do inglês BGA, ball gris array é crítico para o encapsulamento de semicondutores pois uma falha pode gerar rejeitos e retrabalhos indesejáveis ao desempenho da produção. O processo atual da empresa de encapsulamentos analisada apresentou, de forma acumulada, entre os meses de janeiro a junho de 2015 uma taxa de 1220 defeitos por milhão de unidades produzidas, relacionadas ao modo de falha denominado tamanho da esfera com o código SB003. Matérias primas alternativas para aplicação em processo de soldagem de esferas em encapsulamento de semicondutores de diferentes fabricantes, podem apresentar melhor desempenho com relação a esta ocorrência. A redução das perdas de material e de defeitos no processo de soldagem de esferas é essencial para que uma empresa de encapsulamento de semicondutores se mantenha competitiva financeiramente no mercado tanto nacional quanto internacional. O objetivo deste trabalho foi avaliar através de análises de laboratório e aplicações práticas, quatro opções de fluxos de solda solúveis ou parcialmente solúveis em água. Foram comparadas as características de viscosidade, índice de acidez, pH e perda de massa através de TGA do inglês thermogravimetric analysis, aprimorando o conhecimento intrínseco sobre este material e seu comportamento nesta etapa. Foi analisado o impacto dos diferentes fluxos de solda no desempenho da soldagem, realizando a observação da ação do fluxo em um forno de refusão e a habilidade de realinhar esferas de solda fora de posição que impactam na redução da ocorrência de defeitos. Obteve-se como resultado o fluxo A com melhor performance para realinhamento, 9,58% das esferas foram reposicionadas, perda de massa gradual e menos abrupta que os demais. / The process of soldering spheres in ball grid array components, called BGA, is critical to the semiconductor packaging, because one failure can generate rejects and undiserable reworks to production performance. The current process of the packaging company analyzed presented, in accumulated form, between the months of january and june of 2015 the defect rate of 1220 defects per million of produced units, related to the failure mode denominated ball size with the code SB003. Alternative raw material for solder sphere process applied to semiconductor packaging of different manufacturer could show better performance related to these occurrence. The reduction of material waste and defects reduction in the soldering spheres process is essential to keep a semiconductor packaging company competitive financially both in the national and international market. The objective was to evaluate through laboratory analysis and practical applications four options of soldering flux water and non-water soluble. Characteristics were compared of viscosity, acidity level, pH and mass loss through thermogravimetric analysis TGA improving the intrinsic knowledge about this material and its behavior in the step. The impact was analyzed of different solder flux performance on soldering, performing observation of the flux action on the reflow oven and the ability to realign the solder spheres misplaced that impact on the reduction of the occurrence of defects. It was obtained as result the flux A with better performance of realignment, 9.58% of misplaced spheres were repositioned, present gradual mass loss and less abrupt than the others.

Currently the trend of electronic product development is to ward ¡§light and thin, multi-functional, high density and durability¡¨. When the microelectronic chips tend to be high power, high density and high speed, the rapid increase of heat in a reduced unit area of package size, will lead to failure of electronic products. The contents of thesis is to find out the dominant factors in heat transfer by changing the geometries and material properties of QFN and BGA packages. It also aims to achieve the beat the thermal performance by reducing the probability of failure. In industries it needs a lot of cost and time in experiment work due to the changes of size and materials. Herein, the softwares of ANSYS and ICEPAK are adopted to model the QFN and BGA packages with the statistical experimental design of Taguchi method L18 (21¡Ñ37) orthogonal array setting parameters and obtain the degree of effect for each factor. Eventually, we use the analysis of variance ANOVA to obtain the contribution of each factor and to identify the significant degree for various parameters by variance error integration. From the results the die attach thermal conductivity affects the contribution of thermal performance up to 81.46% for QFN package in comparison with other controlling factors of high significance and high impact effects. Die attach thermal conductivity between 0.5 W/m•k and 1.5 W/m•k the Tj declines much larger than that between 1.5 W/m•k and 8 W/m•k. Die /PKG area ratio affects the contribution of the thermal performance to 64.24% and increasing Die /PKG area ratio can reduce the Tj for BGA package. The significant effect is also higher than other factors. However, the contribution of substrate layers is 18.83% at 99% confidence level.

ABSTRACT This thesis gathered the actual Burn-In (BI) data from one of the leading cooperation in the semiconductor industry, and analyzed the major factors¡¦ impact on BGA package solder ball deformation. The Taguchi Method was used for these analyses, and the commercial statistic software MiniTab14 was widely used on this thesis. The solder ball stress was analized by using the commercial FEM software Ansys 8.1. Some electrical characters (such as device power) can be only observed from Burn-In process, but not static acceleration tests. These effects were fully discussed in this thesis. The analyses got the result that the smaller solder ball pitch/solder ball diameter causes the more serious solder ball deformation under the specific socket vendor precondition. Burn-In time are also a significant factor for solder deformation. Basically the longer BI time cause the more serious solder deformation. The device power effect is not significant within the power sampling range of this thesis.

Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

This thesis deals with rework of BGA components. There are described defects and errors in a solder joints. The current trend is focused on thin packages with fine pitch. It is assembled with smaller and smaller solder balls. It is described effect of different application of flux and solders paste for rework. The main part is focused on dipping and dispensing. These methods are suitable for repair process.

Cette thèse, qui s'intègre dans le cadre du projet européen EMCOMIT, a pour objectif de contribuer à l'étude des circuits imprimés haute densité d'intégration comportant un nombre de couches important et des composants enterrés. La qualification de cette technologie est effectuée en conduisant des simulations et des mesures électriques sur des véhicules de tests spécifiques. L'analyse des résultats électriques permet d'évaluer l'aptitude de ces matériaux à répondre aux exigences des applications de télécommunication et de technologie de l'information rapide. La fiabilité d'un assemblage de BGA de grande taille sur un circuit imprimé a été évaluée. Des simulations thermomécaniques ont été effectuées afin de calculer les contraintes résiduelles accumulées pendant le procédé d'assemblage puis l'énergie dépensée dans les parties critiques des joints au cours d'un cycle thermique. Simultanément, des BGA reportés sur des circuits imprimés ont été placés dans une chambre climatique et ont subi des variations de températures.

abstract: Using stereo vision for 3D reconstruction and depth estimation has become a popular and promising research area as it has a simple setup with passive cameras and relatively efficient processing procedure. The work in this dissertation focuses on locally adaptive stereo vision methods and applications to different imaging setups and image scenes. Solder ball height and substrate coplanarity inspection is essential to the detection of potential connectivity issues in semi-conductor units. Current ball height and substrate coplanarity inspection tools are expensive and slow, which makes them difficult to use in a real-time manufacturing setting. In this dissertation, an automatic, stereo vision based, in-line ball height and coplanarity inspection method is presented. The proposed method includes an imaging setup together with a computer vision algorithm for reliable, in-line ball height measurement. The imaging setup and calibration, ball height estimation and substrate coplanarity calculation are presented with novel stereo vision methods. The results of the proposed method are evaluated in a measurement capability analysis (MCA) procedure and compared with the ground-truth obtained by an existing laser scanning tool and an existing confocal inspection tool. The proposed system outperforms existing inspection tools in terms of accuracy and stability. In a rectified stereo vision system, stereo matching methods can be categorized into global methods and local methods. Local stereo methods are more suitable for real-time processing purposes with competitive accuracy as compared with global methods. This work proposes a stereo matching method based on sparse locally adaptive cost aggregation. In order to reduce outlier disparity values that correspond to mis-matches, a novel sparse disparity subset selection method is proposed by assigning a significance status to candidate disparity values, and selecting the significant disparity values adaptively. An adaptive guided filtering method using the disparity subset for refined cost aggregation and disparity calculation is demonstrated. The proposed stereo matching algorithm is tested on the Middlebury and the KITTI stereo evaluation benchmark images. A performance analysis of the proposed method in terms of the I0 norm of the disparity subset is presented to demonstrate the achieved efficiency and accuracy. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Project is focused on describe modern assembly of microelectronic and electronic modules in electronic devices. Sense of the project is analyse reliability and inadequacies electronic devices assembled by modern technogies. Inadequacies modern technologies are impulse for design, implementation and testing new our way of assembly microelectronic modules. Main kind of materials which are used in this project are ceramics Al2O3 and printed circuit board FR4.