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Compensating process and temperature variation in 32nm CMOS circuits with adaptive body biasTariq, Usman, 1982- 21 October 2010 (has links)
As we scale down each process generation the degree of control we have on device parameters decreases. We are left to contend with a great deal of variability in process and environmental parameters. Process variation impacts dopant concentration, channel length, oxide thickness and other device parameters. Temperature variation too affects several parameters, amongst them are the threshold voltage and carrier mobility. All of these variations can either be margined for during design or compensated for dynamically. In this paper the technique of adaptive body bias is successfully applied to compensate for the variation in design so that the circuit operates at no more than 10 percent of the optimal pvt (process voltage temperature) point while minimizing leakage. / text
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Low energy circuit design using low voltage swing and selectively skewed gatesSheshadri, Smitha 29 October 2010 (has links)
In this thesis, we propose a circuit design technique that reduces the energy utilized by any logic circuit for computation. We achieve this, by reducing the voltage swing on the circuit without greatly compromising the
speed of operation and keeping in mind the noise margin constraints. Our technique involves the use of head or tail transistors that provide a Vth drop in the voltage swing. We choose to use head or tail transistors on alternate logic
levels providing us with an option of driver stage, based on the noise margin of the subsequent stage.
We demonstrate the working of this concept on inverter chains, to prove the correctness as well as the ability of the reduced voltage swing circuits to
drive subsequent stages. We also discuss the implementation of this technique on basic gates and simple combinational circuits. We then show detailed experiments on a larger circuit, in this case a Kogge-Stone parallel prefix adder.
We will discuss the overheads involved in the design and methods to partially overcome these by the use of selectively skewed gates and application of forward body bias. Finally we implement the same design using a different
technology to demonstrate the scalability of the technique. / text
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Development of a Multi-Port Memory Generator and Its Application in the Design of Register FilesWang, Chen-Yu 06 September 2011 (has links)
Memory unit is one of the fundamental hardware components in system-on-chip (SoC) design, and takes a significant portion of total area cost. Although commercial memory compilers exist, they usually contains memory unit with single-port or dual ports. However, many SoC designs require memory units that support simultaneous multiple reads and writes. They cannot be efficiently generated using the existing memory compilers in the standard cell library. In this thesis, we develop a memory generator that can automatically produce the circuits of multi-port SRAM and all the necessary models required in the standard cell-based design flow. Compared to the design based on dual-port SRAM from memory compilers which usually consists of duplicated copies of SRAM units for supporting multiple write at the same, the proposed design has smaller area cost. Furthermore, we employ various low-power design concepts, including power-gating and adaptive body-bias, to reduce the dynamic and static power of the generated SRAM circuits. Experimental results show that the proposed multi-port SRAM generator can be used to synthesize low-power and low-area register file circuits that support multiple reads and writes at the same time.
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Design and implementation of a sub-threshold wireless BFSK transmitterPaul, Suganth 15 May 2009 (has links)
Power Consumption in VLSI (Very Large Scale Integrated) circuits is currently a
major issue in the semiconductor industry. Power is a first order design constraint in many
applications. Several of these applications need extreme low power but do not need high
speed. Sub-threshold circuit design can be used in these cases, but at such a low supply
voltage these circuits exhibit an exponential sensitivity to process, voltage and temperature
(PVT) variations. In this thesis we implement and test a robust sub-threshold design flow
which uses circuit level PVT compensation to stabilize circuit performance. This is done
by dynamic modulation of the delay of a representative signal in the circuit and then phase
locking it with an external reference signal.
We design and fabricate a sub-threshold wireless BFSK transmitter chip. The transmitter
is specified to transmit baseband signals up to a data rate of 32kbps over a distance
of 1000m. In addition to the sub-threshold implementation, we implement the BFSK transmitter
using a standard cell methodology on the same die operating at super-threshold voltages
on a different voltage domain. Experiments using the fabricated die show that the
sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based
implementation.
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Design and implementation of a sub-threshold wireless BFSK transmitterPaul, Suganth 10 October 2008 (has links)
Power Consumption in VLSI (Very Large Scale Integrated) circuits is currently a
major issue in the semiconductor industry. Power is a first order design constraint in many
applications. Several of these applications need extreme low power but do not need high
speed. Sub-threshold circuit design can be used in these cases, but at such a low supply
voltage these circuits exhibit an exponential sensitivity to process, voltage and temperature
(PVT) variations. In this thesis we implement and test a robust sub-threshold design flow
which uses circuit level PVT compensation to stabilize circuit performance. This is done
by dynamic modulation of the delay of a representative signal in the circuit and then phase
locking it with an external reference signal.
We design and fabricate a sub-threshold wireless BFSK transmitter chip. The transmitter
is specified to transmit baseband signals up to a data rate of 32kbps over a distance
of 1000m. In addition to the sub-threshold implementation, we implement the BFSK transmitter
using a standard cell methodology on the same die operating at super-threshold voltages
on a different voltage domain. Experiments using the fabricated die show that the
sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based
implementation.
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Modeling, Characterization and Compensation of Performance Variability using On-chip Monitor Circuits for Energy-efficient LSI / オンチップモニタ回路を用いたLSI特性ばらつきのモデル化技術及び補償技術の活用によるエネルギー効率向上に関する研究Islam A.K.M. Mahfuzul 23 January 2014 (has links)
京都大学 / 0048 / 新制・課程博士 / 博士(情報学) / 甲第17992号 / 情博第514号 / 新制||情||91(附属図書館) / 80836 / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 小野寺 秀俊, 教授 佐藤 高史, 教授 松山 隆司 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM
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Extraction of the active acceptor concentration in (pseudo-) vertical GaN MOSFETs using the body-bias effectHentschel, R., Wachowiak, A., Großer, A., Kotzea, S., Debald, A., Kalisch, H., Vescan, A., Jahn, A., Schmult, S., Mikolajick, T. 10 October 2022 (has links)
We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al₂O₃ dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices. Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.
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Robust Design of Variation-Sensitive Digital CircuitsMoustafa, Hassan January 2011 (has links)
The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to
12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors
(ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more
difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the
devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process
variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric
yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random
Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower
power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that
the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design.
Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating
voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We
develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for
die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be
used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the
knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology
prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS
technology.
The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control
the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data
causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power
dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of
secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of
super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these
flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful
recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while
taking the process variations impact and robustness requirements into account.
Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward
body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases
Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and
less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each
device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a
large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for
within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability
and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of
previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital
converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real
microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability
(NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and
test chip measurements using triple-well 65nm CMOS technology.
The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process
variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We
propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative
capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access
yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of
the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results
and test chip measurements using 65nm CMOS technology.
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Robust Design of Variation-Sensitive Digital CircuitsMoustafa, Hassan January 2011 (has links)
The nano-age has already begun, where typical feature dimensions are smaller than 100nm. The operating frequency is expected to increase up to
12 GHz, and a single chip will contain over 12 billion transistors in 2020, as given by the International Technology Roadmap for Semiconductors
(ITRS) initiative. ITRS also predicts that the scaling of CMOS devices and process technology, as it is known today, will become much more
difficult as the industry advances towards the 16nm technology node and further. This aggressive scaling of CMOS technology has pushed the
devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as process
variations, radiation induced soft errors, and aging degradation mechanisms. These new design challenges have a strong impact on the parametric
yield of nanometer digital circuits and also result in functional yield losses in variation-sensitive digital circuits such as Static Random
Access Memory (SRAM) and flip-flops. Moreover, sub-threshold SRAM and flip-flops circuits, which are aggravated by the strong demand for lower
power consumption, show larger sensitivity to these challenges which reduces their robustness and yield. Accordingly, it is not surprising that
the ITRS considers variability and reliability as the most challenging obstacles for nanometer digital circuits robust design.
Soft errors are considered one of the main reliability and robustness concerns in SRAM arrays in sub-100nm technologies due to low operating
voltage, small node capacitance, and high packing density. The SRAM arrays soft errors immunity is also affected by process variations. We
develop statistical design-oriented soft errors immunity variations models for super-threshold and sub-threshold SRAM cells accounting for
die-to-die variations and within-die variations. This work provides new design insights and highlights the important design knobs that can be
used to reduce the SRAM cells soft errors immunity variations. The developed models are scalable, bias dependent, and only require the
knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit optimization as well as technology
prediction. The derived models are verified using Monte Carlo SPICE simulations, referring to an industrial hardware-calibrated 65nm CMOS
technology.
The demand for higher performance leads to very deep pipelining which means that hundreds of thousands of flip-flops are required to control
the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data
causing the overall system to malfunction. In addition, the flip-flops power dissipation represents a considerable fraction of the total power
dissipation. Sub-threshold flip-flops are considered the most energy efficient solution for low power applications in which, performance is of
secondary importance. Accordingly, statistical gate sizing is conducted to different flip-flops topologies for timing yield improvement of
super-threshold flip-flops and power yield improvement of sub-threshold flip-flops. Following that, a comparative analysis between these
flip-flops topologies considering the required overhead for yield improvement is performed. This comparative analysis provides useful
recommendations that help flip-flops designers on selecting the best flip-flops topology that satisfies their system specifications while
taking the process variations impact and robustness requirements into account.
Adaptive Body Bias (ABB) allows the tuning of the transistor threshold voltage, Vt, by controlling the transistor body voltage. A forward
body bias reduces Vt, increasing the device speed at the expense of increased leakage power. Alternatively, a reverse body bias increases
Vt, reducing the leakage power but slowing the device. Therefore, the impact of process variations is mitigated by speeding up slow and
less leaky devices or slowing down devices that are fast and highly leaky. Practically, the implementation of the ABB is desirable to bias each
device in a design independently, to mitigate within-die variations. However, supplying so many separate voltages inside a die results in a
large area overhead. On the other hand, using the same body bias for all devices on the same die limits its capability to compensate for
within-die variations. Thus, the granularity level of the ABB scheme is a trade-off between the within-die variations compensation capability
and the associated area overhead. This work introduces new ABB circuits that exhibit lower area overhead by a factor of 143X than that of
previous ABB circuits. In addition, these ABB circuits are resolution free since no digital-to-analog converters or analog-to-digital
converters are required on their implementations. These ABB circuits are adopted to high performance critical paths, emulating a real
microprocessor architecture, for process variations compensation and also adopted to SRAM arrays, for Negative Bias Temperature Instability
(NBTI) aging and process variations compensation. The effectiveness of the new ABB circuits is verified by post layout simulation results and
test chip measurements using triple-well 65nm CMOS technology.
The highly capacitive nodes of wide fan-in dynamic circuits and SRAM bitlines limit the performance of these circuits. In addition, process
variations mitigation by statistical gate sizing increases this capacitance further and fails in achieving the target yield improvement. We
propose new negative capacitance circuits that reduce the overall parasitic capacitance of these highly capacitive nodes. These negative
capacitance circuits are adopted to wide fan-in dynamic circuits for timing yield improvement up to 99.87% and to SRAM arrays for read access
yield improvement up to 100%. The area and power overheads of these new negative capacitance circuits are amortized over the large die area of
the microprocessor and the SRAM array. The effectiveness of the new negative capacitance circuits is verified by post layout simulation results
and test chip measurements using 65nm CMOS technology.
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Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) / Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOIMhira, Souhir 13 April 2018 (has links)
Cette thèse porte sur la conception et le test des premiers circuits CMOS auto-adaptatifs nanométriques dédiés aux applications automobiles, avioniques et aérospatiales, dans des environnements à forte contrainte car soumis à des compromis entre vitesse (performance), consommation (Low Power) et vieillissement (Wearout). Des solutions innovantes ont été développées avec des boucles de régulation dynamiques pour optimiser la consommation des différents éléments (niveau de conception) et des blocs (système), tout en assurant leur bon fonctionnement. La validation des solutions a été réalisée étape par étape dans la chaîne de conception, en se concentrant d'abord sur le développement d'un premier démonstrateur en technologie CMOS (M40) 40 nm pour les applications automobiles de STMicroelectronics. Différentes manières d'anticiper les erreurs ont été comparées en conservant la détection de retard IS2M dans les chemins critiques. Une modélisation théorique des boucles de contrôle a abouti à un outil de simulation basé sur des chaînes de Markov discrètes dans le temps (DTMC). Cette modélisation a été confrontée avec succès à des mesures de silicium démontrant que les solutions sélectionnées offraient une réduction de la puissance consommée par 2 avec des performances et une fiabilité égales. Dans la dernière partie, les solutions proposees sont testees sur un demonstrateur CMOS FDSOI 28nm, afin de valider la pertinence de l'adaptation dynamique (D-ABB) dans les tensions d'alimentation et de face. / This thesis deals with the design and testing of the first self-adaptive nanoscale CMOS circuits dedicated to automotive, avionics and aerospace applications, under high stress environment because they are subject to the trade-off between speed (performance), consumption (Low Power) and aging (Wearout). Innovative solutions have been developed with dynamic control loops to optimize the consumption of the various elements (design level) and blocks (system), while ensuring their smooth operation. Validation of solutions has been achieved step by step in the design chain, focusing first on the development of a first demonstrator in 40nm CMOS (M40) technology for automotive applications from STMicroelectronics. Various ways of anticipating errors were compared by retaining the IS2M (adjustable time window) delay detection in critical paths as the most efficient for optimization solutions. A theoretical modeling of the control loops has resulted in a simulation tool based on time discrete Markov chains (DTMC). This modeling was successfully confronted with silicon measurements demonstrating that the solutions selected offered a reduction in the power consumed by 2 with equal performance and reliability. In the last part, the high-level hierarchical modeling was applied on several systems / products of 28nm FDSOI CMOS nodes (28FD), in order to validate the relevance of the dynamic adaptation (D-ABB) in supply and face voltages. (VDD, VB). This allowed to prove the validity of the complete methodology by arriving at the precise statistical prediction of the reliability integrating the whole performance-consumption value chain using the advanced simulations.
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