Dans les technologies CMOS avancées, les défauts microscopiques localisées à l'interface Si (Nit) ou dans l'oxyde de grille (Nox) dégradent les performances des transistors CMOS, en augmentant le bruit de basse fréquence (LFN). Ces défauts sont généralement induits par le processus de fabrication ou par le vieillissement de l'appareil sous tension électrique (BTI, porteurs chauds). Dans des transistors canal SiGe ou III-V, leur densité est beaucoup plus élevé que dans le silicium et leur nature microscopique est encore inconnue. En outre, en sub 10 nm 3D comme nanofils, ces défauts répartis spatialement induisent des effets stochastiques typiques responsables de la "variabilité temporelle" de la performance de l'appareil. Cette nouvelle composante dynamique de la variabilité doit maintenant être envisagée en plus de la variabilité statique bien connu pour obtenir circuits fonctionnels et fiables. Aujourd'hui donc, il devient essentiel de bien comprendre les mécanismes de piégeage induites par ces défauts afin de concevoir et fabriquer des technologies CMOS robustes et fiables pour les nœuds de sub 10 nm. / In advanced CMOS technologies, microscopic defects localized at the Si interface (Nit) or within the gate oxide (Nox) degrade the performance of CMOS transistors, by increasing the low frequency noise (LFN). These defects are generally induced by the fabrication process or by the ageing of the device under electrical stress (BTI, Hot Carriers). In SiGe or III-V channel transistors, their density is much higher than in silicon and their microscopic nature still is unknown. In addition, in sub 10nm 3D like nanowires, these spatially distributed defects induce typical stochastic effects responsible for “temporal variability” of the device performance. This new dynamic variability component must now be considered in addition of the well-known static variability to obtain functional and reliable circuits. Therefore today it becomes essential to well understand the trapping mechanisms induced by these defects in order to design & fabricate robust and reliable CMOS technologies for sub 10nm nodes.

L’industrie microélectronique arrive aujourd’hui à concevoir des transistors atteignant quelquesdizaines de nanomètres. A de telles dimensions, les problématiques de fiabilité et de variabilité des dispositifsprennent une ampleur toujours plus importante. Notamment, le couplage de ces deux difficultés nécessite uneétude approfondie pour garantir des estimations correctes de la durée de vie des dispositifs. Aujourd’hui, ladégradation BTI (pour Bias Temperature Instability), due principalement aux mécanismes de piégeage dansl’oxyde de grille, apparait comme étant la principale source de dégradation responsable du vieillissement destransistors. Ce manuscrit présente une étude complète de la dégradation BTI intervenant sur des transistors depetites et grandes dimensions et sur des cellules mémoires SRAM (pour Static Random Access Memory). Dansun premier temps, une présentation des différentes méthodes de caractérisations rapides permettant demesurer correctement cette dégradation est faite. L’importance de l’utilisation de techniques de mesuresrapides afin de limiter les effets de relaxation qui succèdent à la dégradation BTI est clairement exposée. Puis, àl’aide de ces techniques de mesures, une étude exclusivement consacrée à la caractérisation et la modélisationde la dégradation NBTI (pour Negative BTI) sur des dispositifs de grandes dimensions est réalisée. Ensuite, lemanuscrit se focalise sur la dégradation intervenant dans des dispositifs de petites dimensions : transistors etcellules mémoires. Tout d’abord, une modélisation des phénomènes de piégeages dans l’oxyde de grille depetits transistors est effectuée. En particulier, des simulations 3D électrostatiques ont permis d’expliquerl’influence des pièges d’oxyde sur la tension de seuil (VT) dans des transistors décananométriques. Enfin, uneétude de la fiabilité de cellules SRAM est présentée. Notamment, nous montrons comment évoluent lesperformances et le fonctionnement des cellules lorsque les transistors qui les constituent sont affectés par unedégradation BTI. / Nowadays, microelectronic industry is able to manufacture transistors with gate length down to 30nm.At such scales, the variability and reliability issues are a growing concern. Hence, understanding the interplaybetween these two concerns is essential to guarantee good lifetime estimation of the devices. Currently, theBias Temperature Instability (BTI), which is mostly due to the carrier trapping occurring in the gate oxide,appears to be the principal source of degradation responsible for the ageing of transistor device. Thismanuscript presents a complete study of the BTI degradation occurring on small and big transistors and onStatic Random Access Memory (SRAM) cells. Thus, as a first step, several electrical characterization techniquesto evaluate the BTI degradation are presented. The necessity of fast measurement in order to avoid most of therelaxation effect occurring after the BTI stress is emphasized. Then, using these fast measurement techniques,a complete study of the Negative BTI (NBTI) on large devices is presented. Then, the manuscript focuses on thesmall devices: transistors and memory cells. First, a modeling of the trapping mechanism in the gate oxide ofsmall transistor is presented. In particular, 3D electrostatic simulations allowed us to understand the particularinfluence of the traps over the threshold voltage (VT) of the small transistors. Finally, the case of the SRAM isstudied. Finally, the impact of the degradation occurring at transistor level and impacting the functioning of theSRAM bitcells is investigated.

L’industrie microélectronique arrive aujourd’hui à concevoir des transistors atteignant quelquesdizaines de nanomètres. A de telles dimensions, les problématiques de fiabilité et de variabilité des dispositifsprennent une ampleur toujours plus importante. Notamment, le couplage de ces deux difficultés nécessite uneétude approfondie pour garantir des estimations correctes de la durée de vie des dispositifs. Aujourd’hui, ladégradation BTI (pour Bias Temperature Instability), due principalement aux mécanismes de piégeage dansl’oxyde de grille, apparait comme étant la principale source de dégradation responsable du vieillissement destransistors. Ce manuscrit présente une étude complète de la dégradation BTI intervenant sur des transistors depetites et grandes dimensions et sur des cellules mémoires SRAM (pour Static Random Access Memory). Dansun premier temps, une présentation des différentes méthodes de caractérisations rapides permettant demesurer correctement cette dégradation est faite. L’importance de l’utilisation de techniques de mesuresrapides afin de limiter les effets de relaxation qui succèdent à la dégradation BTI est clairement exposée. Puis, àl’aide de ces techniques de mesures, une étude exclusivement consacrée à la caractérisation et la modélisationde la dégradation NBTI (pour Negative BTI) sur des dispositifs de grandes dimensions est réalisée. Ensuite, lemanuscrit se focalise sur la dégradation intervenant dans des dispositifs de petites dimensions : transistors etcellules mémoires. Tout d’abord, une modélisation des phénomènes de piégeages dans l’oxyde de grille depetits transistors est effectuée. En particulier, des simulations 3D électrostatiques ont permis d’expliquerl’influence des pièges d’oxyde sur la tension de seuil (VT) dans des transistors décananométriques. Enfin, uneétude de la fiabilité de cellules SRAM est présentée. Notamment, nous montrons comment évoluent lesperformances et le fonctionnement des cellules lorsque les transistors qui les constituent sont affectés par unedégradation BTI. / Nowadays, microelectronic industry is able to manufacture transistors with gate length down to 30nm.At such scales, the variability and reliability issues are a growing concern. Hence, understanding the interplaybetween these two concerns is essential to guarantee good lifetime estimation of the devices. Currently, theBias Temperature Instability (BTI), which is mostly due to the carrier trapping occurring in the gate oxide,appears to be the principal source of degradation responsible for the ageing of transistor device. Thismanuscript presents a complete study of the BTI degradation occurring on small and big transistors and onStatic Random Access Memory (SRAM) cells. Thus, as a first step, several electrical characterization techniquesto evaluate the BTI degradation are presented. The necessity of fast measurement in order to avoid most of therelaxation effect occurring after the BTI stress is emphasized. Then, using these fast measurement techniques,a complete study of the Negative BTI (NBTI) on large devices is presented. Then, the manuscript focuses on thesmall devices: transistors and memory cells. First, a modeling of the trapping mechanism in the gate oxide ofsmall transistor is presented. In particular, 3D electrostatic simulations allowed us to understand the particularinfluence of the traps over the threshold voltage (VT) of the small transistors. Finally, the case of the SRAM isstudied. Finally, the impact of the degradation occurring at transistor level and impacting the functioning of theSRAM bitcells is investigated.

Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

Made available in DSpace on 2014-06-12T16:26:29Z (GMT). No. of bitstreams: 2 arquivo2154_1.pdf: 2946293 bytes, checksum: d55db8fd95c353e5369e10a31bb5a187 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / A dengue é atualmente considerada a mais importante arbovirose que afeta o homem. O agravamento desta situação epidemiológica tem acarretado um aumento expressivo no uso de inseticidas organofosforados no combate ao vetor, principalmente o temefós, que é amplamente e sistematicamente aplicado em ambientes urbanos em reservatórios de água, até para o consumo humano. Este projeto propôs investigar efeito genotóxico (clastogênico) em células de mamíferos, induzido pela exposição ao temefós (grau técnico 95,5%), e ao biolarvicida Bacillus thuringiensis sorovar. israelenses (Bti) - IPS 82, ambos empregados no controle do Aedes aegypti. Na avaliação genotóxica foram utilizadas células da medula óssea de camundongos albinos Swiss Webster de ambos os sexos, empregando-se os testes de metáfase e de micronúcleos para detecção dos danos cromossômicos: aberrações cromossômicas e micronúcleos. Os camundongos foram tratados com temefós (grau técnico 95,5%) nas concentrações de 27,75; 55,5 e 111 mg/kg ou com água destilada 10 ml/kg, via gavagem, como controle negativo ou com Ciclofosfamida a 25 mg/kg, via i.p., como controle positivo por 24, 48 e 72h, em dose única ou em 9 doses repetidas (1 dose/semana). Outros grupos foram tratados com Bti nas doses de 204 e 122,4 UFC (Unidade Formadora de Colônia) ou água destilada (200 μl) como controle negativo, via gavagem, por 24 e 48h. Os resultados observados confirmaram a ação genotóxica induzida pelo inseticida temefós em camundongos de ambos os sexos, com a formação de micronúcleo em eritrócitos policromáticos (PCE MN), em todas as concentrações testadas 24h após o tratamento único. Na concentração de 111,00 mg/kg induziu PCE MN também após 48 e 72h em dose única e após tratamento com 9 doses. O temefós induziu também aberrações cromossômicas nas células em metáfases, em todas as concentrações testadas, 24h após tratamento único, e na concentração de 111,00 mg/kg, também após 48 e 72h de tratamento único. A Ciclofosfamida padronizada como controle positivo, para detecção de genotoxicidade, assegurou a confiabilidade dos experimentos realizados nos padrões estabelecidos. O Bti, através dos experimentos realizados, não induziu formação de micronúcleos, portanto, não foi considerado como um agente mutagênico e/ou genotóxico. A citotoxicidade do Bti também foi avaliada em diferentes doses e tempos de permanência em ambos o sexo, não apresentando diferença estatisticamente significativa ao nível de 5% em comparação com o controle negativo. Esta investigação veio comprovar a preocupação pelos potenciais riscos que o uso sistemático, constante ou mesmo esporádico de inseticidas de síntese em ambiente antropico, na agricultura e em programas de controles de vetores, pode induzir ao homem ao nível mutagênico e/ou genotóxico. É imprescindível, para o uso seguro para a saúde e o meio ambiente, a investigação do potencial mutagênico e/ou genotóxico de produtos utilizados para o controle de insetos

L’avantage de cette architecture FDSOI par rapport à l’architecture Si-bulk est qu’elle possède une face arrière qui peut être utilisée comme une deuxième grille permettant de moduler la tension de seuil Vth du transistor. Pour améliorer les performances des transistors canal p (PMOS), du Germanium est introduit dans le canal (SiGe) et au niveau des sources/drain pour la technologie 14nm FDSOI. Par ailleurs, la réduction de la géométrie des transistors à ces dimensions nanométriques fait apparaître des effets de design physique qui impactent à la fois les performances et la fiabilité des transistors.Ce travail de recherche est développé sur quatre chapitres dont le sujet principal porte sur les performances et la fiabilité des dernières générations CMOS soumises aux mécanismes de dégradation BTI (Bias Temperature Instability) et par injections de porteurs chauds (HCI) dans les dernières technologies 28nm et 14nm FDSOI. Dans le chapitre I, nous nous intéressons à l’évolution de l’architecture du transistor qui a permis le passage des nœuds Low-Power 130-40nm sur substrat silicium à la technologie FDSOI (28nm et 14nm). Dans le chapitre II, les mécanismes de dégradation BTI et HCI des technologies 28nm et 14nm FDSOI sont étudiés et comparés avec les modèles standards utilisés. L’impact des effets de design physique (Layout) sur les paramètres électriques et la fiabilité du transistor sont traités dans le chapitre III en modélisant les contraintes induites par l’introduction du SiGe. Enfin le vieillissement et la dégradation des performances en fréquence ont été étudiés dans des circuits élémentaires de type oscillateurs en anneau (ROs), ce qui fait l’objet du chapitre IV. / The subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability.

Au sein de la course industrielle à la miniaturisation et avec l’augmentation des exigences technologiques visant à obtenir plus de performances sur moins de surface, la fiabilité des transistors MOSFET est devenue un sujet d’étude de plus en plus complexe. Afin de maintenir un rythme de miniaturisation continu, des nouvelles architectures de transistors MOS en été introduite, les technologies conventionnelles sont remplacées par des technologies innovantes qui permettent d'améliorer l'intégrité électrostatique telle que la technologie FDSOI avec des diélectriques à haute constante et grille métal. Malgré toutes les innovations apportées sur l’architecture du MOS, les mécanismes de dégradations demeurent de plus en plus prononcés. L’un des mécanismes le plus critique des technologies avancées est le mécanisme de dégradation par porteurs chauds (HCI). Pour garantir les performances requises tout en préservant la fiabilité des dispositifs, il est nécessaire de caractériser et modéliser les différents mécanismes de défaillance au niveau du transistor élémentaire. Ce travail de thèse porte spécifiquement sur les mécanismes de dégradations HCI des transistors 28nm FDSOI. Basé sur l’énergie des porteurs, le modèle en tension proposé dans ce manuscrit permet de prédire la dégradation HC en tenant compte de la dépendance en polarisation de substrat incluant les effets de longueur, d’épaisseur de l’oxyde de grille ainsi que l’épaisseur du BOX et du film de silicium. Ce travail ouvre le champ à des perspectives d’implémentation du model HCI pour les simulateurs de circuits, ce qui représente une étape importante pour anticiper la fiabilité des futurs nœuds technologiques. / As the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps.

O trabalho propõe um circuito para caracterização estatística do fenômeno Bias Temperature Instability (BTI). O circuito tem como base uma matriz de transistores para caracterização eficiente em larga escala de BTI. O design proposto visa o estudo da variabilidade de BTI dependente do tempo em dispositivos altamente miniaturizados. Para tanto se necessita medir centenas de dispositivos, a fim de se obter uma amostra estatisticamente significante. Uma vez que variações nos tempos de estresse e medida dos dispositivos podem gerar erros no processo de caracterização, o circuito implementa em chip (on-chip) o controle dos tempos de estresse e de medida, para que ocorra uma caracterização estatística precisa. O circuito de controle implementado faz com que todos dispositivos testados tenham os mesmos tempos de estresse e os mesmos tempos de recuperação (relaxamento). Desta forma, o circuito proposto melhora significantemente tanto a área utilizada quanto o tempo de medida, quando comparado a alternativas anteriormente implementadas. O leiaute do circuito foi realizado no novo nó tecnológico de 28 nanômetros do IMEC. / This work proposes an array-based evaluation circuit for efficient and massively parallel characterization of Bias Temperature Instability (BTI). This design is highly efficient when studying the BTI time-dependent variability in deeply-scaled devices, where hundreds of devices should be electrically characterized in order to obtain a statistically significant sample size. The circuit controls stress and measurement times for accurate statistical characterization, making sure all the devices characterized have the same stress and recovery times. It significantly improves both area and measurement time. The circuit layout is laid out in the new 28nm node IMEC technology.