Testing is an integral part of modern semiconductor industry. The necessity of test is evident, especially for low-yielding processes, to ensure Quality of Service (QoS) to the customers. Testing is a major contributing factor to the total manufacturing cost of analog/RF systems, with test cost estimated to be up to 40% of the overall cost. Due to the lack of low-cost, high-speed testers and other test instrumentation that can be used in a production line, low-cost testing of high-frequency devices/systems is a tremendous challenge to semiconductor test community. Also, simulation times being very high for such systems, the only possible way to generate reliable tests for RF systems is by performing direct measurements on hardware. At the same time, inserting test points for such circuits while maintaining signal integrity is a difficult task to achieve. The proposed research develops a test strategy to reduce overall test cost for RF circuits. A built-in-test (BIT) approach using sensors is proposed for this purpose, which are designed into high-frequency circuits. The work develops algorithms for selecting optimal test access points, and the stimulus for testing the DUT. The test stimulus can be generated on-chip, through efficient design reuse or using custom built circuits. The test responses are captured and analyzed by on-chip sensors, which are custom designed to extract test response features. The sensors, which have low silicon area overhead, output either DC or low frequency test response signals and are compatible to low-speed testers; hence are low-cost. The specifications of the system are computed using a set of nonlinear models developed using the alternate test methodology. The whole approach has been applied to a RF receiver at 1 GHz, used as a test vehicle to prove the feasibility of the proposed approach. Finally, the method is verified through measurements made on a large number of devices, similar to an industrial production test situation. The proposed method using sensors estimated system-level as well as device-level specifications very accurately in the emulated production test environment with a significantly smaller test cost than existing production tests.

Les systèmes industriels recouvrent de nombreuses formes. Aujourd'hui, ils sont le plus souvent organisés en réseaux. Les nouvelles technologies de l'information et de la communication apportent un ensemble de moyens supplémentaires pour réaliser des applications ayant un intérêt majeur pour renforcer l'exploitation sûre de ces systèmes et la sécurité des personnes.Parmi ces systèmes industriels, on peut citer les systèmes cyber-physiques (CPS) caractérisés par un grand nombre de variables, des non linéarités et des incertitudes. Leur décomposition en sous-systèmes, permet de les rendre plus facilement gérables et organisés de façon hiérarchique, est fondamentale. Chacun des sous-systèmes est constitué de différents composants remplaçables interconnectés qui réalisent différentes fonctions.Dans cette optique, nous proposons une approche de diagnostic basée sur quatre types de connaissances : fonctionnelle, structurelle, topologique et comportementale.Cette approche qui inclut la détection et la localisation, exploite la représentation des différentes connaissances pour détecter et isoler la source de défaillance. Afin de lever toute ambigüité de localisation, l’adjonction d’un automate temporisé permet, grâce à une analyse temporelle, d’identifier efficacement le ou les composants défectueux. L’approche multimodèle proposée est agencée autour de trois algorithmes.La modélisation et d’analyse des défaillances est illustrée sur un système cyber-physique : le robot de téléprésence "RobAIR". Les différents modèles de connaissances ont été établis avec une démarche d’analyse ainsi que la construction du diagnostiqueur basée sur des signatures préalablement définies.L‘implémentation des algorithmes de détection, d’isolation sous Simulink/ Stateflow de Matlab a permis de construire le diagnostiqueur selon la méthodologie proposée et valider ainsi notre approche par simulation du fonctionnement avec injection de façon aléatoire de différentes défaillances.La méthode d’analyse proposée a été appliquée aux tests de démarrage du robot RobAIR avec une attention particulière sur la partie déplacement. Le test de l’ensemble des fonctionnalités du robot est réalisé par la programmation de la carte Arduino. Pour cette application, les algorithmes de détection et d’isolation ont été complétés par la détection d’obstacle et l’identification du mode défaillance. / Industrial systems cover many forms. Today, they are most often organized in networks. The new information and communication technologies provide a set of additional means to realize applications of major interest to strengthen the safe operation of these systems and the safety of people.Among these industrial systems, we can cite cyber-physical systems (CPS) characterized by a large number of variables, nonlinearities and uncertainties. Their decomposition into subsystems, making them more manageable and hierarchically organized, is fundamental. Each of the subsystems consists of different interconnected replaceable components that perform different functions.With this in mind, we propose a diagnostic approach based on four types of knowledge: functional, structural, topological and behavioral.This approach, which includes detection and localization, exploits the representation of different knowledge to detect and isolate the source of failure. In order to eliminate any ambiguity of location, the addition of a timed automat allows, thanks to a temporal analysis, to efficiently identify the defective component(s). The proposed multimodel approach is organized around three algorithms.Modeling and failure analysis is illustrated on a cyber-physical system: the "RobAIR" telepresence robot. The different knowledge models were established with an analysis approach as well as the construction of the diagnostician based on previously defined signaturesThe implementation of Matlab's Simulink / Stateflow isolation and detection algorithms made it possible to build the diagnoser according to the proposed methodology and thus validate our approach by simulating the operation with random injection of various failures.The proposed analysis method was applied to the RobaIR robot's start-up tests with particular attention to the displacement part. The testing of all the robot's functionalities is done by programming the Arduino board. For this application, the detection and isolation algorithms have been supplemented by obstacle detection and failure mode identification.

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.

This study was conducted in collaboration with BAE Systems Hägglunds in Örnsköldsvik. They wanted help with their objective of researching the necessary components of a testability analysis. The primary goal was to enhance the efficiency of troubleshooting and diagnostics for their combat vehicle, Cv90. As their vehicles become increasingly advanced, troubleshooting can become challenging and time-consuming. An example of a problem that can arise is when an error code is displayed to the crew, but the technicians at the workshop are unable to identify the root cause of the error. To gather information, scientific articles and other relevant documents were extensively reviewed. Additionally, interviews were conducted with employees at BAE. The scope of the study was limited to troubleshooting within a workshop setting, rather than in the field. It was assumed that the troubleshooting equipment and software were functional, and the focus was solely on identifying faulty components. The research was conducted both in Umeå and on-site in Örnsköldsvik. A methodology for implementing a fault detection system with effective testability was developed. This encompassed considerations for the construction and content of the troubleshooting system. Determining the system's requirements and devising methods for testing their fulfillment were crucial aspects. Prioritization of different functions based on their criticality was recommended. Critical functions should be addressed first and may require more costly and intricate solutions. Various approaches to enhance troubleshooting at a more granular level were identified. These included establishing better threshold values, accounting for measurement uncertainties in the test equipment, and emphasizing the importance of a robust test design that considers deviations from system equilibrium. Additionally, worn components were recognized as a potential cause for false indications that are challenging to diagnose. It is important to note that these improved fault detection methods have not yet been implemented in the vehicles. / Studien genomfördes i samarbete med BAE Systems Hägglunds i Örnsköldsvik. De ville få hjälp med sitt mål att undersöka de nödvändiga komponenterna i en testabilityanalys. Det primära målet var att effektivisera felsökning och diagnostisering av deras stridsfordon, Cv90. När deras fordon blir alltmer avancerade kan felsökningen bli utmanande och tidskrävande. Ett exempel på ett problem som kan uppstå är att en felkod visas för besättningen, men teknikerna på verkstaden kan inte identifiera orsaken till felet. För att samla information gjordes en omfattande granskning av vetenskapliga artiklar och andra relevanta dokument. Dessutom genomfördes intervjuer med anställda på BAE. Studiens omfattning var begränsad till felsökning på verkstaden, snarare än i fält. Det antogs att felsökningsutrustningen och programvaran var funktionella, och fokus låg enbart på att identifiera felaktiga komponenter. Arbetet utfördes både i Umeå och på plats i Örnsköldsvik. En metodik för att implementera ett felsökningssystem med god testbarhet utvecklades. Detta omfattade överväganden för felsökningssystemets konstruktion och innehåll. Att bestämma systemets krav och utforma metoder för att testa deras uppfyllnad var avgörande aspekter. Prioritering av olika funktioner baserat på deras kritikalitet rekommenderades. Kritiska funktioner bör åtgärdas först och kan kräva mer kostsamma och invecklade lösningar. Olika metoder för att förbättra felsökning på en mer detaljerad nivå identifierades. Dessa inkluderade att fastställa bättre tröskelvärden, ta hänsyn till mätosäkerheter i testutrustningen och betona vikten av en robust testdesign som tar hänsyn till avvikelser från systemjämvikt. Dessutom identifierades slitna komponenter som en potentiell orsak till felaktiga indikationer som är svåra att diagnostisera. Det är viktigt att notera att dessa förbättrade felsökningsmetoder ännu inte har implementerats i fordonen.

The dissertation thesis with the topic „Simulation Modelling of Electrical Drives for Selected Critical Applications“ focuses on the area of given applications in civil aviation. The selected application that the thesis deals with is an electrically driven and electronically controlled fuel pump supplying fuel to an aviation motor of the APU type. The thesis gives a comprehensive description of the design cycle of the unit and demonstrates implementing all the required critical functions. In the course of the design of the unit modern techniques in mathematical modelling, simulation, verification, monitoring and prediction of the operation status of airborne equipment were uses to the utmost extent. The purpose of these was to show the suitability of their application with regard to decreasing design time and cost, increasing lifetime and servicing intervals, as well as increasing user comfort and decreasing price. At the same time the required reliability was to be kept. The thesis also aims to prove and verify the suitability of using electronically commutated dc motors in critical applications in civil aviation. To reach this goal, it is necessary to design a robust drive control which would meet the given reliability requirements.

The dissertation thesis with the topic „Simulation Modelling of Electrical Drives for Selected Critical Applications“ focuses on the area of given applications in civil aviation. The selected application that the thesis deals with is an electrically driven and electronically controlled fuel pump supplying fuel to an aviation motor of the APU type. The thesis gives a comprehensive description of the design cycle of the unit and demonstrates implementing all the required critical functions. In the course of the design of the unit modern techniques in mathematical modelling, simulation, verification, monitoring and prediction of the operation status of airborne equipment were uses to the utmost extent. The purpose of these was to show the suitability of their application with regard to decreasing design time and cost, increasing lifetime and servicing intervals, as well as increasing user comfort and decreasing price. At the same time the required reliability was to be kept. The thesis also aims to prove and verify the suitability of using electronically commutated dc motors in critical applications in civil aviation. To reach this goal, it is necessary to design a robust drive control which would meet the given reliability requirements.